Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to store a block of data values arranged in a first order. The first circuit may be further configured to present a plurality of the data values in parallel in response to a plurality of address signals, where the data values are presented in a second order. The second circuit may be configured to generate the plurality of address signals in response to a first signal, a second signal and a third signal. The second circuit generally includes an even number of address generators configured to generate the plurality of address signals in parallel.

Abstract: An application programming interface (API) implementation that can interface between an application and a programming library. The implementation includes a Function Router Wrapper that receives a formatted string from the application. The formatted string includes a function name element filled with a function name, an input element filled with function input parameters, and an unfilled output element. The Function Router Wrapper converts the formatted string and passes it to a Function Router, which parses the converted formatted string to access the function name and the function input parameters. The Function Router calls a library function based on the accessed information. When the called library function is completed, the Function Router collects generated function outputs and embeds them into the formatted string output element. The Function Router passes the formatted string back up to the Function Router Wrapper, which converts the formatted string and passes it back up to the application.

Abstract: Methods and systems for managing a device in a Web Based Enterprise Management (“WBEM”) environment. At least a management software component and a device management adapter are reused through receiving a network command from the management software component, and forwarding the network command to the device management adapter for conversion to a device message. The WBEM environment is supported by packaging the device message in a WBEM envelope, and transmitting the device message in the WBEM envelope to a computer system. The computer system comprises the device. Subsequently, a native command based on the device message is issued to the device.

Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.

Abstract: A parameter estimating apparatus for permanent magnet synchronous motor driving system is disclosed, the apparatus estimating an inductance and a magnet flux linkage of a permanent magnet through a real-time magnetic flux estimation, whereby an operation performance of the PMSM can be enhanced.

Abstract: Provided is a regenerative medium voltage inverter, the inverter being such that regenerative operation is enabled by changing structure of input terminal of a unit power cell at a series H-bridge medium voltage inverter, and a dynamic braking resistor is not required to reduce the size of a DC-link capacitor over that of a conventional medium voltage inverter.

Abstract: A method for backing up and restoring data across multiple operating systems executed by a computing product executing computer implemented instructions, wherein each operating system includes a daemon. Embodiments may include receiving a backup initiation trigger from an initial, daemon on an initial operating system. This method may include relaying the backup initiation trigger to other daemons on other operating systems. This method may also include receiving snapshot requests from the other daemons, wherein each of the snapshot requests are requests for snapshots of storage associated with an operating system of one of the other operating systems. This method may further include sending received snapshot requests from the other daemons to a storage controller.

Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

Abstract: A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed.

Abstract: An EtherCAT-based network system configured to change a PDO list set, and an operation method thereof are provided, the system including at least one or more slave devices, a master device configured to connect and operate the slave device in response to an operating transmission PDO list or an operating reception PDO list provided from outside, and a host computer configured to extract the operating transmission PDO list or the operating reception PDO list from information file of the slave device and provide to the master device, wherein the information file includes at least one of identity information of the slave device, PDO list item changeable information, at least one or more transmission PDO list, and at least one or more reception PDO list.

Abstract: Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.

Abstract: A method for performing motion estimation based on at least a first VOP stored in a memory includes the steps of: receiving a request to read a data block indicative of at least a portion of the first VOP for predicting a second VOP that is temporally adjacent to the first VOP; utilizing a DMA module for determining whether the data block is a UMV block; translating a block address for retrieving at least a portion of the data block from the memory as a function of one or more parameters generated by the DMA module; and generating a complete data block as a function of the portion of the data block retrieved from the memory and the one or more parameters generated by the DMA module.

Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

Abstract: A data processing system for processing a video stream comprises memory array circuitry, memory access circuitry, and video processing circuitry. The memory array circuitry is characterized by a width and a height. The memory access circuitry is operative to cause, through a series of write operations, a series of two-dimensional data representations of different respective regions in a frame of the video stream to be stored in the memory array circuitry. The write operations occur such that only data missing from the memory array circuitry is written to the memory array circuitry during each write operation and such that the data is written modulo at least one of the width and the height of the memory array circuitry. Lastly, the video processing circuitry is operative to perform block matching on the video stream at least in part utilizing the series of two-dimensional data representations stored in the memory array circuitry.

Abstract: Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component.

Abstract: Systems and methods for out of order memory management.

Abstract: An apparatus and method for controlling train speed are disclosed, the method including receiving an operation data, estimating a future train speed subsequent to a predetermined time of the train, using the operation data and dynamics model of a train, calculating a TTSLC {Time-To-Speed-Limit Crossing, a time when the train exceeds an ATP (Automatic Train Protection) speed limit}, and outputting a deceleration command by determining an additional braking force, in a case the TTSLC is smaller than a predetermined threshold.

Abstract: A method and circuit to control the intensity of lights, illumination fixtures, and displays using pulses of a fixed duration and a fixed frequency (FD/FF) is provided. In particular, the method may be used to control one more light sources. By varying the number of pulses in a control burst, the total current flowing through the light source may be precisely controlled providing greater accuracy than other methods, such as, for example, PWM or variable pulse frequency. The FD/FF technique may be used in conjunction with any number of light sources, and finds particular application in LED displays and for any type of LED illumination fixture.