Abstract: A method for preparing at least one metal layer of an integrated circuit for visual analysis. The at least one metal layer to be visually analyzed is exposed, and a solution of nitric acid, acetic acid, and ammonium fluoride is applied to the at least one metal layer. The at least one metal layer is rinsed to substantially remove the solution, and the s integrated circuit is dried. The solution is made with one part nitric acid, three parts acetic acid, and two parts ammonium fluoride. The nitric acid is a solution of about seventy percent by weight in water, the acetic acid is glacial acetic acid, and the ammonium fluoride is a solution of about forty percent by weight in water. The solution is at a temperature of about seventy degrees Fahrenheit, and is applied to the at least one metal layer by swabbing the solution onto the layer for between about ten seconds and about fifteen seconds. The step of exposing the at least one metal layer includes sawing the integrated circuit along a desired cross section.

Abstract: A method and apparatus are provided for analyzing test vectors for use in measuring static current consumed by an integrated circuit. A netlist of interconnected cells is read to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes. Once the netlist has been read, cell characteristics for selected ones of the cell types are read from a technology library to identify pins of the selected cell types to be monitored. The nodes in the netlist that correspond to these pins are identified and are added to an list file. Once the list file has been generated, a computer simulation program is used to simulate a steady-state response of a functional model of the integrated circuit to a potential test vector and to output the resulting logic states on the nodes provided in the list file.

Abstract: Provided is a non-destructive method of detecting die crack problems in an integrated circuit. The method provides for testing for die crack problems in all chips and in many production chips without adding any extra circuitry or pads. In a preferred embodiment, the method takes advantage of an existing NAND gate tree structure at the perimeter of many conventional dies, although the invention is also applicable to other logic gate structures that may exist or may be formed at the perimeter of dies. The invention recognizes that this NAND gate tree structure may be used in order to identify and localize die cracks in finished chips, thereby providing a faster, more accurate and nondestructive way to test for die cracks in production chips. A typical NAND gate tree structure has the form of a cascade inverter chain. Since one end of the first NAND gate is tied to VDD, the output of each gate will alternate between low and high.

Abstract: Cell assignment section performs an automatic cell assignment according to circuit data 51. Distribution path determining section automatically determines a distribution path between cells. Distribution information extracting section extracts information regarding already determined distribution path. Prescribed-information recognizing section recognizes information on a prescribed portion (end or bend) of the distribution. Additional-distribution-data generating section generates additional distribution data for correcting the width of the prescribed portion. Additional-distribution-data lay-out section lays out the generated additional distribution data for the prescribed portion. This makes it possible to quickly obtain final pattern data in a state of designing a mask that is used for manufacturing a semiconductor integrated circuit device.

Abstract: A method of pin placement for an integrated circuit includes the steps of (a) receiving as input a corresponding set of pin constraints for each pin of a hard macro, (b) receiving as input a specification for the hard macro, (c) locating pin slots on each side of the hard macro, (d) finding at least one of a horizontal interval and a vertical interval on a side of the hard macro for each pin of the hard macro, and (e) assigning each pin of the hard macro to a pin slot within the horizontal interval and the vertical interval that satisfies the corresponding set of pin constraints.

Abstract: When a mobile communication unit (e.g. a cellular telephone) is powered up, the unit must lock on to a local base station, or “acquire” a base station signal, to enable the user to send and receive calls. To lock on a local base station, the mobile unit must determine the delay at which the base station is sending the pseudo random (PN) code. This process is called the “acquisition.” The current art of acquiring a base station involves collecting a set of samples at a particular code phase, or delay, testing the collected sample, and repeating these steps using another code phase until the correct code phase is found. The present invention discloses a method and apparatus for collecting a set of samples at a particular code phase, and simultaneously testing the collected sample and collecting the next set of samples for another code phase.

Abstract: A receiver for detecting a stream of optical data bits which are transmitted at a predetermined frequency includes a plurality of optically-active devices arranged on an integrated circuit substrate in an array. The plurality of optically-active devices are capable of being positioned to receive the stream of optical data bits which are transmitted as light, and each of the optically active devices is capable of detecting light in an optically active state and generating a detected signal corresponding thereto. A control circuit receives a clock signal at a rate corresponding to the predetermined frequency and generates control signals which cause a different one of the plurality of optically-active devices to be in the optically active state during each successive period and thereby detect the presence of light during each of said successive periods and generate the detected signals corresponding to the data bit stream.

Abstract: Forward error correction apparatus and methods are described. A forward error correction system includes multiplier for computing an erasure location polynomial. An erasure location is applied to an input of a input register. An output of a given register in a series of registers and an output of the input register are multiplied to produce a product. The product and an output of the dummy register are added to produce a sum. The sum is applied to an input of a subsequent register immediately following the given register. The subsequent register is treated as the given register and the above-described steps are repeated for each of the erasure locations. A two-buffer method and apparatus for computing an error location polynomial using the Berlekamp error correction algorithm also is described.

Abstract: A method for assigning signal traces to one of a plurality of power planes on a power layer of an integrated circuit package. The integrated circuit package has an integrated circuit signal contact region, a top routing layer, and a bottom routing layer. The power layer underlies both the top routing layer and the bottom routing layer. First signal traces on the bottom routing layer are routed from contacts disposed in a core portion of the integrated circuit signal contact region to first ball contacts disposed within a first perimeter of the integrated circuit package. The first perimeter has dimension corresponding to a first distance from the integrated circuit signal contact region. Second signal traces on the top routing layer are routed from contacts disposed in a peripheral portion of the integrated circuit signal contact region to second ball contacts.

Abstract: In order to optimise power consumption, an electronic circuit assembly comprises clock means for switching a plurality of gate circuits, the gate circuits including a first gate circuit having a first power consumption as a function of clock frequency, and a second gate circuit performing a similar function as the first circuit and having a second power requirement as a function of frequency, and means for switching off one gate circuit and switching on the other gate circuit in dependence upon the intended frequency of operation. The circuit assembly may be an arithmetical operation circuit or a finite state machine.

Abstract: Methods for designing an integrated circuit is disclosed. In the present invention, the integrated circuit is first created by placing and routing standard cells of the integrated circuit. After routing the standard cells, empty spaces unused by the standard cells are extracted. After extracting the unused areas, clusters of metal-programmable transistors are inserted into the unused areas by an area-based placement/routing tool to form “ponds” of gates (POGs). When design changes are desired after the formation of the integrated circuit, the metal-programmable transistors are programmed to form desired spare cells to implement the desired design changes by making changes to the upper layer masks for the integrated circuit.

Abstract: An apparatus for storing and playing videos. The apparatus includes a storage device containing a video for playback on a user system located on a communications network. The apparatus includes a system connection to a data processing system and a network connection to the communications network. The apparatus includes a transfer means for transferring the video from the storage device to the network using the network connection, wherein the video is directly transferred from the apparatus to the network.

Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells.

Abstract: A method for making a flip chip ball grid array (BGA) package includes the step of thinning a die for matching a composite coefficient of thermal expansion to that of a second level board.

Abstract: An optical disk system is presented which incorporates computer graphics rendering capability to create and display three-dimensional (3-D) objects synchronized with 3-D sound. The optical disk system includes an audio/video (A/V) decoder coupled to a microprocessor and a rendering unit. The A/V decoder and the microprocessor receive a bitstream including encoded video and audio data, 3-D presentation data, and navigation data. The 3-D presentation data includes object and audio modeling data, and may also include instructions executed by the microprocessor in order to perform an operation upon the object and audio modeling data. The object modeling data includes data pertaining to an object to be displayed upon a display device, and the audio modeling data includes data pertaining to sound to be produced by multiple speakers. The bitstream may be a DVD-compliant bitstream having an sub-picture unit (SPU) portion, and the 3-D presentation data may be conveyed using the SPU portion of the bitstream.

Abstract: An integrated circuit includes a vertical-interdigitated capacitor located between an upper interconnect layer and a lower interconnect layer. Both interconnect layers include conductors formed of a metal capable of atom diffusion or ion migration, such as copper. The capacitor plates contact an interconnect layer conductor to create barrier layers to prevent atom diffusion or ion migration from the conductors at the contact locations. Additional barrier layers contact the conductors at locations other than where the capacitor plate portions contact the conductors, and the additional barrier layers are preferably formed of the same material and at the same time that one of the plates is formed. The integrated circuit may include a via plug interconnect extending between conductors of upper and lower interconnect layers, with a plug barrier layer surrounding the plug material to prevent atom diffusion or ion migration from the plug material.

Abstract: The present invention has application to final balancing of an initial balanced clock tree. In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each level of a balanced clock tree. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit.

Abstract: The invention relates to the transmission of telemetry data from a stylus to a host computer via a serial, asynchronous data channel. The telemetry data is encoded into code-words using a specially selected error detecting or error correcting code, the code-words are transmitted from the stylus in a continuous, homogeneous data stream without the use of framing delimiters between adjacent code-words, and the code-words are then received by the host computer which separates the code-words according to the unique characteristics of the selected code. The code may be chosen based on both the error detection/correction requirements of the system and the probability that the code will create invalid intermediate code matches between consecutive back-to-back code-words. In one embodiment, the invention provides a synchronization scheme which greatly reduces the probability that invalid intermediate code matches will be recognized in the host computer as validly transmitted code-words.

Abstract: An RTL back annotator for applying back annotated data to the RTL code of an RTL simulation for verifying actual timing performance for an ASIC array after layout during RTL simulation parses through annotation data from the back annotation file for the ASIC layout and generates RTL delays for each wire and register in the ASIC layout. The RTL annotator then applies the generated RTL delays to the RTL compiled design, thereby emulating the delays that a gate level netlist would have. In this manner, an RTL simulation having timings of the real layout may be run.

Abstract: A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type.