Abstract: In the present invention a nonvolatile memory array architecture can be realized by a fabrication process more compatible to an MOS logic fabrication process as compared with previous nonvolatile memory array architectures. Higher write and/or read speed is possible because of a lower bit line resistance. A high hard bit density near 4F2 is possible when a self-align contact technology and a border less contact technology are used. Connection regions are formed throughout the memory array comprising four cells that are connected to one bit line. The connection regions can be formed in the same processing step with opposite conductivity regions for economy of processing. A plurality of memory cells are two dimensionally disposed in two different directions with connection regions, conductive bit lines extending in the first direction, conductive word lines extending in the second direction, and conductive control lines.

Abstract: The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array.

Abstract: The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array.

Abstract: Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer.

Abstract: An apparatus for planarizing a surface of a semiconductor wafer includes a wafer support configured to receive the semiconductor wafer so that the surface of the semiconductor wafer projects from the wafer support. The apparatus also includes a polishing member configured in the form of an endless unitary belt which is devoid of seams. The endless unitary belt is (i) positioned in contact with the surface of the semiconductor wafer and (ii) capable of moving in a linear direction relative to the surface of the semiconductor wafer so as to planarize the surface of the semiconductor wafer. An associated method of linearly planarizing a surface of a semiconductor is also described.

Abstract: A test signal is propagated through at least a portion of the circuit from a respective input. The test signal is based on a row of a k-wise, &egr;-discrepant matrix. Cells are identified whose outputs have a constant response to the test signal and the inputs of the identified cells are combined with the inputs of the circuit. The process is iteratively repeated until the output of the circuit is reached. The circuit inputs and inputs of identified cells are selected as test points.

Abstract: Methods and associated structure for enabling immediate availability of a disk array storage device. In particular, the methods and associated structure of the present invention permit access to a logical unit of a storage system immediately following creation of the logical unit. Initialization of the logical unit to initialize redundancy information therein proceeds in parallel with host system access to the storage space of the logical unit. The initialization process maintains a boundary parameter value indicative of the progress of the initialization process. Storage space above the boundary has had its redundancy information initialized while storage space below the boundary has not. Where an I/O request is entirely above the boundary, it is processed normally in accordance with the management of the logical unit. Where part of an I/O request is below the boundary, it is processed in a special manner that assures integrity of the redundancy data.

Abstract: A luminaire reflector formed from at least one sheet of reflective material is folded and curved by hand to form a self-standing reflector having a predetermined three-dimensional reflector shape. Each sheet of reflective material includes integral panels that are joined to adjacent panels through fold lines that allow the panels to be folded by hand. The panels have free edges that are folded and/or curved into abutting relationship. The panels include locking members and positioning tabs formed adjacent the free edges to retain the reflector in a predetermined three-dimensional reflector shape. Methods of making a self-standing reflector for a luminaire are also disclosed.

Abstract: The phase locked loop circuit according to the present invention is configured such that the CPU changes the time constant of the variable LPF filter to an optimum value in accordance with the state of the external signal fed from outside, for example by way of a selection switch activated in accordance with a control signal fed from the CPU, the responsive rate of the PLL circuit is raised, so that it can cope with jittery movements generated due to noise or a fluctuation of the supply voltage of the PLL circuit itself.

Abstract: Disclosed is a method of planarizing an array of plastically-deformable electrical contacts on an integrated circuit. An integrated circuit is placed on a plate with an array of plastically-deformable electrical contacts substantially parallel to and facing the plate, thereby creating an assembly. The integrated circuit is placed above the plate such that the weight of the integrated circuit bears down on the array of plastically-deformable electrical contacts. The assembly is then heated sufficiently to cause individual ones of the plastically-deformable electrical contacts to locally soften but not to cause said individual ones of the electrical contacts to liquefy throughout their volumes. The weight of the integrated circuit applies a force to the softened plastically-deformable electrical contacts, thereby resulting in their planarization.

Abstract: A method for measuring electromigration includes the steps of measuring a corresponding voltage increase across an interconnect as a function of time for a plurality of nonzero heating rates and calculating an interconnect integrity from the voltage increase.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: A debug circuit (2) and a microcomputer incorporating the debug circuit (2). The debug circuit (2) is capable of receiving a trace event from a functional block A as long as a CPU (5) does not generate any trace event, and capable of receiving the trace event from the functional block A in synchronization with a standard clock signal CLK used in the CPU (5) when the reception of the trace event from the functional block A is permitted.

Abstract: A testing system includes a controller, a device driver for the controller, and a processor. The controller is operable to control a device coupled thereto. The device driver is operable to provide a generic interface for data transfers to and from the controller. The processor is coupled to coupled to the controller and is operable to execute a test script having a plurality of script commands. Moreover, the processor is operable to transfer test data to the controller via the generic interface of the device driver in response to executing a first script command of the plurality of script commands. The processor is also operable to receive status information from the controller via the controller generic interface.

Abstract: True paths are identified in a timing graph of a circuit in which the timing graph contains known false paths containing nodes of at least two sets selected from FROM, THROUGH and TO nodes. The false paths are processed to include sets of FROM and TO nodes and then transformed into equivalent sets of two logical false paths. True path intervals are constructed as logical subgraphs that do not describe any equivalent false path. In preferred embodiments, the process is carried out by a computer under control of a computer readable program.

Abstract: A system and method for fax transmission over a fax relay network that includes at least a wideband portion and a narrowband portion, includes a first fax relay gateway communicatively connecting a sending fax machine on the wideband portion of the network to the narrowband portion of the network, the first fax relay gateway receiving image data from the sending fax machine and outputting digitized image data in accordance with a data rate of the narrowband portion of the fax relay network. A second fax relay gateway, communicatively connects a receiving fax machine to the narrowband portion of the network. At least one of the first fax relay gateway or the second fax relay gateway includes a control process that determines whether an amount of data stored in a buffer in the fax relay gateway is greater or less than a particular threshold or determines that the amount of jitter in the narrow band network exceeds a particular threshold, and if so, initiates a retrain procedure to adjust the fax data rate.

Abstract: A dual plasma process generates a microwave neutral plasma remote from a semiconductor wafer and a radio frequency (RF) ionized plasma adjacent to the wafer for simultaneous application to the wafer. A first gas flows through a microwave plasma generation area, without a second gas in the gas flow, to generate the neutral microwave plasma. The second gas is added to the gas flow downstream of the microwave plasma generation area prior to an RF plasma generation area.

Abstract: In this method for hierarchical extraction of interconnect parasitic data for integrated circuits, a representation of coupled interconnects and polygon data copied from an upper level to a lower level is simplified so that the coupled interconnects and the polygon data are considered to be ground wires. This method also features instance-specific management of hardmac data from copied hardmac views to create SPEF files using both chip level and macro level back-annotation in a hierarchical representation.

Abstract: The present invention provides a method of memory cell selection and operation to obtain wide program bandwidth and EEPROM erase capability. Two storage sites within a memory cell can be simultaneously selected during read, program and erase. By proper biasing, each of the sites can be independently read and programmed. Also, during program, the source of energy to produce the current flow can be dynamically obtained from the stored charge on the selected bit line. If the bit line capacitance is not adequate to provide a charge that is necessary, additional bit line capacitance is borrowed from unselected bit lines, or a source follower select transistor may be used.