Abstract: The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. A one-dimensional optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.

Abstract: A low-complexity method and apparatus for generating address sequences for the moving inversion test method. In one embodiment, the address sequence generator includes a ring of counter cells in which each cell is configured to provide a toggle signal to a subsequent cell. Each cell receives a distinct least significant bit selector signal which, when asserted, designates the subsequent cell as the least significant bit. When the least significant selector signal is asserted, the cell continuously asserts the toggle signal to the subsequent cell. When the selector signal is de-asserted, the cell asserts the toggle signal to the subsequent cell half as often as the toggle signal from the preceding cell. Each cell provides an output address bit which is toggled whenever the toggle signal from the preceding bit is asserted across a transition in a clock signal. This configuration causes the ring of cells to implement a counter with a selectable least significant bit.

Abstract: A termination impedance in a semiconductor circuit is trimmed to fall within a desired range by a trimming circuit such that the amount of variation in the termination impedance is less than the variation in the sheet rho (resistivity) of the semiconductor. An external reference resistor causes a reference current to flow in multiple branches of a current mirror circuit. One branch of the current mirror circuit has a resistance less than the reference resistor, another has a resistance approximately equal to the reference resistor, and another has resistance greater than the reference resistor. Variation in the sheet rho results voltage drops across the resistor in variation in the resistor values. A logic circuit detects the variations, and encodes a control signal. The control signal is received by a variable termination circuit that switches parallel resistance branches in or out of the termination impedance circuit such that an effective termination impedance is selected based upon the control signal.

Abstract: The present invention is directed to an electrical connector including a first connector pin suitable for making contact on a side of a first flat conductor surrounded by an insulator and a second connector pin suitable for making contact on a side of a second flat conductor surrounded by an insulator. The first flat conductor and the second flat conductor are spaced to form an electrical differential pair.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: A retrofit luminaire assembly for mounting in an existing canopy fixture housing and methods of installing same. The retrofit luminaire assembly includes a planar panel having electrical control elements mounted to an upper surface of the panel. A lamp is received in a lamp socket mounted to the panel with a light-emitting section of the lamp extending away from a lower surface of the panel. A lens is mounted to the lower surface of the panel for enclosing the light-emitting section of the lamp. The panel preferably has a pair of oppositely directed pivot members which are adapted to engage with inwardly directed flanges of the canopy fixture housing to removably and pivotally support the panel for movement between a vertical, inoperative position and a horizontal, operative position. Flange extension members are provided to engage the inwardly directed flanges of the fixture housing to reduce the size of the opening for larger fixture housings to a desired common size opening.

Abstract: In the context of mirror modulation (56, 90, 104) extraction during track seek or jump modes of an optical disc reading device (12), such as a DVD ROM, a mirror averaged level (i.e. the dc level (52) of the RF envelope (34)) is held so that the mirror modulation (90) is seen as a swing below a set mirror rebias level (86) at an output of a mirror amplifier (72), as shown in FIG. 3. With the holding of the dc level (52) by a ground-referred capacitor (302) during seek operation of the device (12), a first input (nin) to the mirror amplifier varies with the mirror modulation, whereas a second input (pin) to the mirror amplifier (72) does not vary. This phenomenon enables the top level of a RFRP signal (82) to be defined by the mirror rebias level (86) and the mirror component swing (during seek operation) to be optimized and always to occur below the mirror rebias level (86).

Abstract: A method of transferring a block of graphics data for display on a screen along a data bus between a processing block and a plurality of addresses in memory comprising the steps of (A) generating a first and a second X and Y coordinate value for each of one or more portions of data to be transferred, (B) calculating a respective address in memory of the plurality of addresses corresponding to each of the first and second coordinate values, (C) accessing the addresses to effect the data transfer, (D) determining if a plurality of bus criteria are met and (E) enabling or inhibiting transfer of the block of data in a data burst in response to the plurality of criterias being met.

Abstract: A method of determining interrupts in data on an optical disc, the data supported in a signal envelope subject to variation by mirror modulation and said interrupts. The method comprises the steps of (A) filtering the signal envelope to generate a first signal; (B) re-biasing the first signal to produce an intermediate signal having voltage swings attributable to the mirror modulation; (C) defining a slice level below a reference level to sample the mirror modulation to produce a mirror signal; (D) slicing the intermediate signal to generate the mirror signal containing a pulse resulting from a level transition through the slice level associated with re-biasing of the positive transition component; and (E) registering the presence of the pulse during the on-track mode of operation to identify the interrupt in data on the optical disc.

Abstract: A digital communications receiver is provided with a PSK demodulator and a soft-decision decoder. The PSK demodulator is configured to accept a receive signal and responsively produce quantized baseband signal components which include a quantized radial component RQ and a quantized angular component &thgr;Q. The soft-decision decoder is coupled to the PSK demodulator to receive the quantized baseband signal components and is configured to convert the quantized signal components into decoded information bits. The soft-decision decoder preferably uses a squared Euclidean distance metric calculation for the decoding process. Using polar coordinate quantization provides an improved performance relative to Cartesian coordinate quantization. A new distance metric for TCM decoding is also provided which requires less implementation complexity than a standards Euclidean distance metric calculation, and which suffers no significant performance loss.

Abstract: A method of efficiently characterizing modules of an integrated circuit (IC) design using a logic synthesis tool comprising the steps of defining a list of instances of the modules to characterize, and characterizing entire modules of said list of instances of the modules using a single invocation of characterize command of the logic synthesis tool.

Abstract: A process is disclosed which inhibits cracking of the layer of low k silicon oxide dielectric material on an integrated circuit structure during subsequent processing of the layer of low k silicon oxide dielectric material. The process comprises: forming a layer of low k silicon oxide dielectric material on an integrated circuit structure on a semiconductor substrate, and forming over the layer of low k silicon oxide dielectric material a capping layer of dielectric material having: a dielectric constant not exceeding about 4, a thickness of at least about 300 nm, and a compressive stress of at least about 3×109 dynes/cm2. In a preferred embodiment, the capping layer comprises silicon oxide formed by reaction of silane and N2O in a PECVD process carried out within a pressure range of from about 600 milliTorr to about 1000 milliTorr; and a temperature range of from about 300° C. to about 400° C.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an intermediate signal in response to an input signal and a first feedback signal. The second circuit may be configured to generate an output signal in response to the intermediate signal and a second feedback signal. The third circuit may be configured to generate the first feedback signal and the second feedback signal in response to the output signal.

Abstract: A differential output buffer includes a differential output stage, first and second push-pull circuits and first and second adjustable, controlled current sources. The differential output stage has first and second differential data outputs and first and second output stage control inputs. The first push-pull circuit has first and second complementary data inputs and has an output coupled to the first output stage control input. The second push-pull circuit has first and second complementary data inputs and has an output coupled to the second output stage control input. The outputs of the first and second push-pull circuits have rise times that are controlled by the first controlled current source and fall times that are controlled by the second controlled current source.

Abstract: A data serializer includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n data inputs. Each pair of first and second control inputs is driven by first and second logic AND circuits having p-channel output drive transistors.

Abstract: Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and.

Abstract: A method of stably and uniformly erasing a non-volatile memory or memory array in a gate insulator in which carrier-trapping sites for carrier storage are furnished is described. A first method of the invention is the application of a discharge pulse(s) to a gate after erasure where the discharge pulse(s) discharges unstable holes injected into the gate insulator. A second method of the invention is injection of electrons into the trap sites of all the cells in a memory array to be erased before erasure. This makes Vth distribution across the memory array uniform after erasure. A third method of the invention is a reduced bias approach to erase stably the electrons stored in the trap sites. This includes not only literally “erase,” but also “annihilate or neutralize” trapped electron charge by hole charge.

Abstract: A process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive material from the upper surface of the dielectric layer, wherein the improvements comprise: a) before the planarizing step, forming over the second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the first electrically conductive material; and b) then planarizing the structure to remove: i) the planarizable material; ii) the second electrically conductive material; and iii) the first electrically conductive material; above the upper surface of the dielectric material; whereby the planarizable material above the second electrically conductive material in the trenche

Abstract: A substantially vertical interdigitated plate capacitor, formed in interlayer dielectric material between upper and lower interconnect layers of conductors in an integrated circuit, comprising a lower plate that has at least one U-shaped portion and a horizontal portion connected to an upper edge of the U-shaped portion. The capacitor's upper plate also has at least one U-shaped portion positioned within the interior of the lower plate's U-shaped portion and a horizontal portion connected to an upper edge of each vertically extending leg. The integrated circuit incorporating the capacitor comprises a via connection having a U-shaped layer extending between the conductors of the relatively upper and relatively lower interconnect layers and is formed simultaneously with one of the U-shaped portions of the capacitor plates.

Abstract: A system for silicon chip evaluation comprising a chip embedded in a wafer and one or more testbench circuits embedded in the wafer, wherein the one or more testbenches provide verification of the chip. One aspect of the present invention concerns a method for silicon chip verification comprising the steps of (A) embedding a chip in a silicon wafer, (B) embedding one or more testbench circuits in the silicon wafer, and (C) communicating between the one or more testbenches and the chip to provide silicon verification of the chip.