Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer.

Abstract: A ventilation unit for operative arrangement within an electronic apparatus. This unit has: an exterior side having a first exhaust port separated from, and located in stacked relationship with, a second exhaust port; and a first and second powered air mover, each having an intake side oriented at an angle greater than zero degrees from the exterior side. The first powered air mover intake side is in communication with the first exhaust port. One powered air mover can be located closer to the exterior side than the other. Gas, such as air, removed from the electronic apparatus can be drawn in through an intake side of the second powered air mover, then directed through a duct cover before it flows between a covered side of the first powered air mover and a support member side of the unit. The angle of orientation is preferably between twenty and one-hundred degrees. Additional powered air movers can be accommodated, each with a respective exhaust port.

Abstract: An integrated circuit providing selectable power supply lines for isolating defects manifested by unusual quiescent current levels. During normal operation, a unitary power supply line provides power to different sections of the integrated circuit. In accordance with the present invention, the unitary power supply line is decoupled from the sections of the integrated circuit and power is provided by the selectable power supply lines during failure analysis of the integrated circuit. A section of interest of the integrated circuit is first placed in a static test state in which defects in the section may produce unusual quiescent current levels. A selectable power supply line for providing power only to the specified section of the integrated circuit is the activated by an enable signal provided to a switch coupled to the selectable power supply line. The switch allows for decoupling of the unitary power supply line from the selectable power supply line.

Abstract: A charge pump includes a main pump circuit having a main first and second switching transistors and an auxiliary pump circuit. The charge pump is configured to provide a variable bias to at least the first switching transistor in response to operation of the auxiliary pump circuit. The auxiliary pump circuit can include auxiliary first and second switching transistors corresponding to the first and second switching transistors of the main pump circuit. The auxiliary first and second switching transistors control a charging level for auxiliary charge storage. A bias transistor of a controllable current source for the first switching transistor of the auxiliary pump circuit is responsive to a charging level of the auxiliary charge storage to provide a self-regulating bias to the first switching transistor of the auxiliary pump circuit.

Abstract: A processor is provided which performs relative addressing using the exception program counter. In one embodiment, a pipelined processor is provided with an exception program counter (EPC) register chain for tracking exception re-entry points in the instruction stream, and the instruction pipeline is provided with access to at least one of the registers in the register chain. The pipeline includes a fetch stage, a decode stage, and an execute stage. The exception PC register is identified by the decode stage as an operand in a memory access instruction for the execute stage to operate on. The execute stage then adds the contents of the exception PC register to the contents of a processor register or to a literal value to determine a target memory address.

Abstract: A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.

Abstract: In a semiconductor integrated circuit, I/O buffer circuits that include ESD protection are generally provided for each I/O pad. According to the invention, unused pads, i.e. pads that are not connected to core circuitry according to an initial design, are connected to other pads that are used for connection to the core circuitry, thereby employing the unused pads to improve ESD protection of susceptible pads. This approach has the advantages of greater ESD protection without increasing silicon area and without adding any additional steps to the usual fabrication process. The inventive concept is especially useful for augmenting ESD protection of corner pads without requiring new or custom ESD protection circuits. This invention can be easily implemented into known layout tools.

Abstract: A method and apparatus for equalizing the frequency response of a transmission line is provided. The method includes the steps of modelling the frequency response of the transmission media for a predetermined frequency range to a predetermined accuracy; determining a desired equalizer response by taking an inverse of the modelled frequency response of the first step; implementing an equalizer that exhibits the desired response; and utilizing the equalizer to equalize the frequency response of the transmission line. The apparatus includes an adaptive equalizer circuit which includes a plurality of signal processor circuits which each take an input signal from the transmission line and process it to mimic a term in a transfer function which represents an inverse of the transfer function of the transmission line. The signals from these processors are then summed and multiplied by a programmable gain term. Then the input is added to the output of the multiplier to form an output equalizer signal.

Abstract: A multiple-sized integrated circuit (IC) die and a method of making a multiple-sized IC die includes forming a plurality of IC dies on a semiconductor wafer. Each IC die has multiple rows of bonding pads around its periphery. Adjacent bonding pads on separate rows of each IC die are electrically connected together so that attachment to any one of the connected bond pads yields the same result. A plurality of scribe streets separate each IC die on the wafer, with the scribe street defining the width between each IC die. Rows of bonding pads reside in the scribe street area. Different rows of bonding pads may be selectively removed from the IC die by scribing the wafer so as to include one or more of the rows of bonding pads, thereby allowing one IC die design to have multiple sizes. An IC die separated from the wafer may still be sized smaller as long as there remain at least two rows of bonding pads around the periphery.

Abstract: A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.

Abstract: A device and method to control a node within a network is disclosed. The node can have any number of ports N where N is an integer greater than one. The device has N-port modules, corresponding to the number of ports in the node, each port module associated with one port for controlling reception and transmission of information through the associated port. The port modules are substantially identical and the device can be manufactured by replicating N-port modules, one port module for each port. The port modules have a priority within the node. The priority can be created by connecting the port modules in a daisy chain configuration. The port module having the highest priority compares the unique identifier of the node with the unique identifier being received by the port associated with the highest priority port module. The results of this comparison are sent to the next highest priority port module.

Abstract: A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising: a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Also, a PLL circuit for recovering a clock signal from incoming data, comprising: a clock generator for generating an odd number, n, of phase-shifted adjacent clock signals; a data sampler for sampling the incoming data; a first pair of outputs from the sampler, for use in a phase detector (along with a reference clock of the adjacent clock signals and the incoming data), capable of producing an adjustment output.

Abstract: The present invention includes a method of lessening or suppressing a transient voltage comprising the step of biasing an output node for an output signal. The step of biasing includes a charge rate that is variable to lessen or suppress the transient, which can be audible. A node is biased to a voltage that corresponds to a voltage of an input signal. Preferably, the node is biased prior to providing the output signal. The present invention also includes a device for lessening a transient of an amplifier comprising a switch coupled to an output of the amplifier and a bias voltage source, wherein the switch is controllable to bias the output prior to the amplifier providing an amplified audio signal. The resistance of the switch can be variable to adjust the lessening of, or suppress, the transient. Instead of the switch, an impedance device can be used. The present invention contemplates lessening or suppressing the transient by either adjusting the charge rate or the bias voltage of the node.

Abstract: In this invention a reference circuit is disclosed that produces a reference current to be used in determining the value of data in a flash memory cell. The memory cell current is compared to the reference current in a sense amplifier. A reference circuit that generates the reference current is connect to each bit line of the flash memory and uses bit lines that are not activated when a particular cell is being read to connect the reference current to the sense amplifiers. The use of a reference current allows multi-bit cells to be read by using a variation on the reference circuit that has a plurality of reference transistors creating a plurality of reference currents.. Verification of the programmed and erase states of a flash memory cell can be determined using different values of the reference current that are easily set in the reference circuit by changing a reference voltage.

Abstract: A controllable reactance implemented within an integrated circuit includes a first sub-circuit (20) comprising a reactive element, for example a capacitor 12, coupled in series with a transistor (14). A controllable current source (16) injects a controllable bias current through the transistor (14) to vary the effective resistance of the transistor (14) and hence the effective complex impedance of the capacitor combination. A second transistor (18) amplifies the current to increase the effective capacitance. Preferably, a second sub-circuit (24) includes corresponding components (26, 28, 30) to mirror the real component of the current flowing in the first sub-circuit (20), and transistors (32 and 34) to reflect an inverse current to the coupling node line (22) to cancel the real component of the current at the node, to thus simulate a purely capacitive circuit. An oscillator embodying this circuit is also disclosed.

Abstract: A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. A placement improvement operation such as simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge.

Abstract: Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.

Abstract: A process is disclosed for forming vias and trenches in two separate dielectric layers, which may be separated by an etch stop, while avoiding the etch mask stress complicated resist masks, or high aspect ratio openings of the prior art. A first dielectric layer 10 is formed over an integrated circuit structure 2 on a semiconductor substrate, and a thin second dielectric layer 20 is formed over the first dielectric layer. A first resist mask, is formed over the second dielectric layer, and the first and second dielectric layers are etched through to form one or more vias 18, 28 extending through both the first and second dielectric layers. The first resist mask is then removed and a third dielectric layer 70, having different etch characteristics than the second dielectric layer, is deposited over the structure.

Abstract: A method of testing a semiconductor device includes generating a current waveform for the semiconductor device by measuring the response of the device to an initializing vector group and comparing the current waveform to a golden waveform to determine whether the semiconductor device is good or defective. Apparatus for testing the semiconductor device includes a vector generator providing an initialization vector group to the semiconductor device, a measurement unit for measuring a plurality of current measurements from the semiconductor device which responds to the input of the initialization vector group, a generation unit for generating a current waveform from the current measurements of the semiconductor device, and an analysis unit for comparing the current waveform to a golden waveform to determine whether the device falls outside a tolerance margin of the golden waveform.

Abstract: Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i.e.