Abstract: The present invention addresses the problem of describing an arbitrary object (up to user-defined limits) given a set of triangles with vertex normals describing the object. A novel method of successively merging traingles into larger and larger patches to compute a set of "as-few-as-possible" Bezier patches is presented. This method is not only applicable to arbitrary objects, but also aims at producing as few patches as possible depending on the geometry of the input object. Also presented are methods to enforce C.sup.0 - and C.sup.1 -continuity between a pair of patches B.sub.L (s,t) and B.sub.R (s,t), placed arbitrarily. The methods perturb the appropnate control points to achieve geometric continuities. For C.sup.0 -continuity the area of the hole between the patches is minimized by formulating the area as a series of linear programs, where the continuity has to be enforced across the adjacent boundary curves B.sub.L (1,t) and B.sub.R (0,t). Similarly, to enforce C.sup.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. Because of the large number of cells and nets of an IC, the process of determining IC delay of an IC design requires a lot of time. The present invention discloses a method and apparatus for determining the IC delay quickly by using multiple processors and analyzing multiple pins simultaneously. Also disclosed is the method of ordering the pins to allow the application of the parallel processing technique.

Abstract: The system and method of the present invention enable the effective and efficient determination of the misalignment between openings located in the contact layer and the interconnect layer, respectively. In this way, defective semiconductors produced in semiconductor wafer fabrication can be readily identified and segregated for shipment to customers. A single multifunctional structure formed in the contact layer can be used to determine the alignment accuracy of the contact layer and the interconnect layer by (a) inline visual inspection and (b) determination of the end of line electrical resistance properties of the semiconductor wafer. Hence the use of the multi-functional aspects of this invention eliminates the correlation issues with the structure.

Abstract: A network in a memory device for selecting a bit line during a data read or a data write. The network includes a first bit line in communication with a bitcell and a second bit line in communication with the bitcell. A charger is in communication with the first and second bit lines, and the charger is configured to charge the first bit line to a first charged level and the second bit line to a second charged level before a data read or a data write. A sensor is connected to the first and second bit lines. The bitcell drives one bit line up and the other bit line down during a data read. The sensor senses a difference between the first and second bit lines to select one of the first and second bit lines during a data read.

Abstract: A retrofit luminaire assembly for mounting in an existing canopy fixture housing and methods of installing same. The retrofit luminaire assembly includes a planar panel having electrical control elements mounted to an upper surface of the panel. A lamp is received in a lamp socket mounted to the panel with a light-emitting section of the lamp extending away from a lower surface of the panel. A lens is mounted to the lower surface of the panel for enclosing the light-emitting section of the lamp. The panel preferably has a pair of oppositely directed pivot members which are adapted to engage with inwardly directed flanges of the canopy fixture housing to removably and pivotally support the panel for movement between a vertical, inoperative position and a horizontal, operative position. Methods of installing the retrofit luminaire assembly in the existing canopy fixture housing are also disclosed.

Abstract: The problems outlined above are in large part solved by an improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The front end includes a frequency synthesizer with an externally configurable charge pump on the tuner chip. The charge pump is coupled to a tank circuit having an adjustable resonance frequency. The resonance frequency can be adjusted over an entire octave by controlling the reverse bias voltage on a pair of varactors. A charge pump with a configurable gain is used to provide a control voltage to the tank circuit to provide a constant phase locked loop response over the frequency range of the tank circuit. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip is coupled to receive a receive signal and convert it to a baseband signal. The tuner chip includes an externally configurable charge pump, a tuning oscillator, and a downconverter.

Abstract: A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle.

Abstract: The plurality of memory cells of a dynamic random access memory (DRAM) are formed in a well of one majority carrier type, and the well is located in a substrate of the other majority carrier type. The well electrically isolates the memory cells from electrical noise signals created by current in the substrate and charged carriers created by alpha particles. The well is connected at multiple spaced-apart locations to a referencing conductor, to maintain the well at a uniform potential in response to noise. The memory cells are formed in a single well, or groups of the memory cells are each formed in a separate well. A shielding conductor, such as the mesh or an integrally continuous layer of metal which is spaced from the memory cells, overlays a matrix of the memory cells and shields then from the effects of noise.

Abstract: A method for transferring data from a first clock domain to a second clock domain. A first clock signal is generated for the first clock domain from a base clock signal. A second clock signal is generated for the second clock domain from the base clock signal. A phase relationship is detected between the first clock signal and the second clock signal. Data is transferred from the first clock domain to the second clock domain using the phase relationship between the first clock signal and the second clock signal.

Abstract: Semiconductor integrated circuits are electrically marked at final test time to form a permanent, visually and electrically readable record of the test results. The electrical record can provide a simple good/bad indication, i.e. indicate whether or not the device passed final test. This provides for more efficient handling of failed devices returned from the field, as the manufacturer can immediately determine whether the device in question passed final test before shipment--or inadvertently "escaped" from the manufacturer. The electrical marking technique, preferably using one or more fuses on board the device, can be used to record quiescent current test, speed sort test and various other final test results. These and other test results recorded on the chip are useful to quality and reliability studies, and in reducing the time and effort required to determine the failure mode of a returned device.

Abstract: A semiconductor chip fabrication assembly and method including a semiconductor package having a packaging substrate and a semiconductor die. An active circuit surface of the semiconductor die is positioned adjacent to a contact surface of the packaging substrate such that a substantially thin gap is formed therebetween. A semi-rigid shroud device is provided which defines a vacuum chamber configured to extend around the gap to hermetically seal the gap within the vacuum chamber. A dispensing device is provided having an outlet end positioned proximate the gap in the vacuum chamber which is adapted to vacuum flow the bonding material between the electrical contacts in the gap, and between the active circuit surface and the contact surface. The absence of air and any other gases forms a substantially voidless underfill layer of bonding material in the gap.

Abstract: In the manufacture of Printed Circuit (PC) boards, conductors are placed in a base layer of glass cloth. The conductors penetrate the thickness of the cloth and can be arranged to form a matrix or grid. The arrangement of cloth and conductors is then cured with resin with the wire lengths disposed within the cured board core. The wire lengths can be made flush with the board core surfaces and become the electrical conductors between circuitry on such surfaces. In one embodiment, the wire is removed leaving a finished hole ready for standard through-hole plating. These finished circuit boards can be stacked and laminated forming through, blind, or buried vias. One or more finished circuit boards with imbedded vias can be used as circuitry redistribution layers to avoid dense circuit patterns in applications such as in flip-chip mounting of integrated circuit chips. In another embodiment, the conductors are imbedded in the glass cloth with sufficient density to form a composite thick conductor.

Abstract: An Integrated Circuit (IC) wafer test fixture includes a baseplate and a top plate. During testing, an IC wafer is positioned between the baseplate and top plate with annular rubber gaskets, forming sealed cavities above and below the IC wafer. A fluid pressure generator with a pressure gauge inserts a fluid under pressure into one of the cavities, causing the IC wafer to be subject to stress. The fluid distributes a uniform pressure load on the surface of the IC wafer. The pressure of the fluid may be gradually increased until a desired pressure is obtained or the wafer fails. The pressure at failure is recorded, and by calculation the failure stress of the IC wafer can be determined. A second embodiment of the test fixture includes a pressure vessel with a threaded sealed opening at the top and a stepped sealed opening at the bottom. The inner diameter of the insert is sized for an IC wafer. In use, the IC wafer is positioned on top of the insert, and the pressure vessel is sealed.

Abstract: Format-independent electronic circuit descriptions are generated by providing incompatible sets of naming conventions, providing translation rules for generating circuit element names which satisfy all supported naming conventions, and modifying element names in accordance with the translation rules. Supported circuit descriptions may represent netlists defined by high-level design languages such as Verilog, EDIF, VHDL, and so forth, or may represent schematics or other symbolic representations. Any element associated with any input circuit representation may be tested or modified to ensure compatibility, such as the naming of logic cell types and instances, the naming of nets interconnecting logic cells, and the naming of input, output, and bidirectional ports. In a preferred embodiment, an element name to be resolved is inserted into a set of element names to determine whether the name is unique. If not, the proposed name is modified according to a set of modification rules until uniqueness is achieved.

Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.

Abstract: A method for efficient, high quality rendering of a surface patch. The method tests a surface patch for flatness, and if the surface patch is not flat, the method divides the surface patch into a left surface patch and a right surface patch. Otherwise if the surface patch is flat, the method converts the surface patch into triangles. This method can be implemented to operate recursively, thereby ensuring that all portions of the patch are eventually converted into triangles when the portions become small enough to satisfy the flatness condition. A patch tests as flat only if all curves which form the patch do not deviate from straight lines by more than a predetermined tolerance. The division is efficiently performed by determining (i) left patch control points for a first portion of all curves along one axis of the surface patch, and (ii) right patch control points for a second portion of all curves along said axis of the surface patch.

Abstract: The present invention includes a modeling and testbench creation methodology which will allow a simulator to provide information regarding the state and direction of a bi-directional pad or pin. The present invention provides ATE tools all of the required data used to accurately and efficiently check for tester compatibility for which test patterns are extracted. In particular, the present invention includes a method of modeling a bi-directional I/O pad that includes the steps of providing a first signal in a first model; providing a second signal in a second model; and determining contention and direction of a resolved signal that is generated in response to at least one of the input and output signals. The first signal is a preferred output signal that is contained within an ASIC (first) model. The second signal is a preferred input signal that is contained within a testbench (second) model.

Abstract: The invention comprises an integrated circuit structure, and a process for making same, comprising a via/contact opening in a dielectric layer; a CVD layer of titanium nitride having a thickness of at least about 50 Angstroms, but not exceeding about 200 Angstroms, on the sidewall and bottom surfaces of the via/contact opening to provide adherence of the filler material to the underlying and sidewall surface of the opening; a CVD barrier layer of tungsten, having a thickness of about 50 Angstroms, but not exceeding about 300 Angstroms, formed over the titanium nitride layer; and the remainder of the via/contact opening filled with a highly conductive metal selected from the group consisting of copper, CVD aluminum, and force-filled aluminum.

Abstract: A system arbitrator for a multi-function device is disclosed. The access arbitrator includes a bus access counter and comparator which are used to generate a bus request disable signal. The bus request disable signal for each function of the multi-function device is gated with the bus request signal for the function. As a function transfers data over the system bus, the access counter is incremented. When the access counter is incremented to a value which equals a predetermined maximum, the bus request disable signal becomes active and disables generation of bus requests for the function. In order to enable the bus signal generator for a function to begin generating bus requests, the access counters are reset when no bus request signals are being generated by any of the bus signal generators.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which preserves frequency offset error tracking through a channel change. The demodulator/decoder receives the baseband signal and produces a compensation signal for canceling the frequency offset error. This is done using an element which generates a value indicative of the frequency offset error. Since the frequency offset error is independent of the selected channel, freezing the value indicative of the frequency offset error during a channel change enables a much faster acquisition of timing.