Abstract: Methods of etching optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed.

Abstract: A semiconductor device package for one or more semiconductor dice uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the top traces and the bottom traces. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits. The core circuits and the input-output circuits may be powered by the same power supply or separate power supplies.

Abstract: A complex, say, N=5 or greater input terminal, mask decoder circuit which is useful in the design of ALUs in microprocessors is presented. The circuit avoids wiring and uses logic gates to make the connections between the input terminals receiving the control bit signals and the output terminals on which the mask signals are generated. This allows the mask decoder circuit to occupy a minimal amount of space on an integrated circuit.

Abstract: A process is provided for use with a semiconductor testing apparatus having a vector generator which provides a sequence of vectors to a semiconductor device at a rate responsive to a timeset, a power supply which provides current to the semiconductor device and a current monitor which measures the current provided to the device. In one specific embodiment, the process includes setting the timeset to a first rate, conditioning the device by executing a plurality of vectors at the first rate, setting the timeset to a second rate, the second rate being slower than the first rate, and measuring the quiescent current while the timeset is set to the second rate.

Abstract: An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.

Abstract: An electrical circuit and method combine junction field effect transistors (JFET) and metal oxide semiconductor (MOS) circuits in series between V.sub.DD and ground, with a feedback of output voltage to control current from V.sub.DD to ground. The electrical circuit comprises a complementary metal oxide semiconductor (CMOS) inverter circuit with an input and an output, and a JFET having a gate coupled to the CMOS inverter for feedback to control the JFET. The JFET and CMOS circuitry is formed on a common substrate with the JFET gate junction being formed by implanting impurity dopants through a layer of gate oxide.

Abstract: A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

Abstract: A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data values. An address decoder receives an address for accessing n data values at a time from the memory modules and asserts address values to access corresponding rows of the first and second memory modules. Select logic selects between respective columns of the first and second memory modules to retrieve the desired data values according to a predetermined order. A shift network reorders the retrieved data values, if necessary, to place them in the proper order for the processing array. The address decoder provides a select value to the select logic and a shift value to the shift network for each cycle. For purposes of horizontal decimation, the pixel values are organized into an even and an odd group, which groups are stored in the memory buffer in two separate regions separated by an address offset K.

Abstract: A computer-based method is provided for determining whether a semi-conductor device conforms to design requirements. In one embodiment, the method is based on data stored in a design database, and an automatic test equipment ("ATE") datalog. In a further embodiment, the method includes generating a requirements datalog responsive to the design database, generating a standard datalog responsive to the automatic test equipment datalog, and generating a conformance indication responsive to the requirements datalog and the standard datalog.

Abstract: A polishing pad conditioner has a grid with an abrasive surface for conditioning a polishing pad. Opposite the abrasive side of the grid, there is a back surface, having at least one key way, which extends at least partially into the back surface. A grid holder has a number of keys equal to the number of key ways in the back surface of the grid. The grid holder keys engage the grid key ways, thereby eliminating slippage between the grid and the grid holder. A mechanized arm is attached to the grid holder, and imparts a rotational and translational motion to the grid holder. A magnet may be used as an attachment means between the grid and the grid holder. The key ways of the grid and the keys of the grid holder may be arranged such that the grid holder can only receive the grid with the back surface of the grid facing the grid holder.

Abstract: A single chip hub for an electronic communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for processing the packets, and a plurality of media access interfaces. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface.

Abstract: A system for designing an integrated circuit with multiple functions is disclosed. The system creates a set of files defining a structure for a plurality of functions existing within one integrated circuit. Floorplanning modifications are then permissible within any functional block, as well as from one functional block to another since the files for each integrated circuit chip are reconfigureable upon modification. The subject invention also provides for floorplanning modifications involving multiple integrated circuit chips wherein any one functional block may be moved from one integrated circuit chip to another to achieve better optimization with less restrictions.

Abstract: An integrated circuit fabrication method and apparatus to improve the design cycle time for implementing an electrical system in silicon. The invention uses predefined core, or cell, patterns to provide some of the functionality for a system design. The cores are interconnected using thick wire conductors and solder bumps so that conductive paths that do not lie within the plane of the substrate of the silicon chip containing the cores are provided. Since the conductive paths do not lie on the process surface of the chip, the topographical design of the chip is not affected by the interconnections. Further, the thick wire conductors result in essentially zero propagation delay so that timing design errors are greatly reduced, or eliminated, in the design cycle. The invention allows for a rapid prototype of the entire design to be produced early in the design cycle. In one embodiment, customer logic is arranged around the periphery of the substrate while the core cells are in the middle of the substrate.

Abstract: A process and resulting product are described for forming an integrated circuit structure with horizontal fuses on an insulation layer formed over other portions of the integrated circuit structure by forming rectangular recesses in the insulation layer which are subsequently filled during a subsequent metal deposition step which also serves to fill with the same metal vias or contact openings which have been etched through the insulation layer. Subsequent planarization of the deposited metal layer down to the vias or contact openings, i.e. to remove the portions of the metal layer over the insulation layer, leaves the metal in the vias or contact openings and also leaves metal stringers on the sidewalls of the rectangular recess which then serve as fusible links (fuses) which are then connected to one or more metal lines thereafter formed on the insulation layer.

Abstract: A canopy luminaire (10, 110, 210) for mounting by a single individual in a canopy comprises a luminaire housing (12, 112, 212) having a bulbous body (14, 114) configured to receive the light-emitting section of a lamp and a narrow neck (16, 116). Spring clips (26, 124) are secured to opposing sides of the narrow neck (16, 116) and are adapted to support the luminaire (10, 110) from a canopy. A locking component (31) may be attached to the narrow neck (16, 116) to fixedly secure the luminaire (10, 110, 210) to the canopy. The luminaire (10, 110, 210) may also include externally mounted control gear (80), such as the ballast. Further, the luminaire (10, 110, 210) may include a hingedly attached glass lens (42) to permit quick and easy replacement of lamps. Alternatively, luminaire (210) may include a rotatably attached glass lens (240).

Abstract: A process is disclosed for forming trenches having high surface-area sidewalls with undulating profiles. Such trenches are formed by first implanting multiple vertically separated layers of dopant in a substrate beneath a region where the trench is to be formed. Next, the trench is formed under conditions chosen to selectively attack highly doped substrate regions (i.e., substrate regions where the dopant has been implanted). The resulting trench sidewalls will have undulations corresponding to the positions of the implanted regions. In one case, the implanted layers contain germanium ions, and a trench is aniostropically etched through the layers of germanium. Thereafter, the trench is subjected to oxidizing conditions to form regions of germanium oxide. Finally, the trench is exposed to an aqueous solvent which dissolves germanium oxide, disrupting the silicon lattice, and leaving gaps or undulations in the sidewall.

Abstract: A method and apparatus for isolating faults in an integrated circuit reduces time and effort to precisely locate such faults. A fault dictionary is developed, which is a record of the errors a circuit's modeled faults are expected to cause. The fault dictionary need only be generated once, and can be recalled for later testing of the same design. A failing circuit is subjected to test vectors and the erroneous outputs are logged, and then all failing scan test vectors are mapped into simulation scan patterns. Faults in the circuit are localized to a more narrowly defined area in which faults in the circuit may occur. If the area, even after localization, is too large, additional test patterns are developed and the device is subjected to another round of tests. The redefinition of test patterns is repeated until possible fault locations are sufficiently localized. The device is then probed to precisely locate the fault(s).

Abstract: Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing.

Abstract: An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.