Abstract: A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.

Abstract: Apparatus and process for making the apparatus for electrostatic discharge (ESD) protection of an electronic device, using a silicon controlled rectifier (SCR) configuration. A spaced apart p-well and n-well are formed in a substrate, and spaced apart p+ and n+ contact regions are formed in each well, with an additional n+ or p+ drain tap contiguous to and lying between the two wells. The wells may be formed by a retrograde process or by a conventional process, with or without an epitaxial layer. A first electrode (ground) is connected to the p+ and n+ contact regions and through a polysilicon region to a gate oxide region in the first well. The polysilicon region has a small, controlled poly length. A second electrode is connected to the p+ and n+ contact regions in the second well and to an electrical circuit to be protected against ESD. The second well may be replaced by a portion of the substrate, of opposite electrical polarity to the first well.

Abstract: The present invention describes a method for detecting thickness measurement error of a film mounted on a wafer substrate. The method comprises exposing a film to be measured to electromagnetic waves over a range of incident wavelengths, reflecting the electromagnetic waves from an outer surface of the film and from the film-substrate interface so that said reflected electromagnetic waves interfere with one another, and measuring an intensity of the reflected electromagnetic waves. A reflected intensity curve is then computed over the range of incident wavelengths and then compared to a theoretically calculated reflected intensity curve to obtain a goodness of fit (GOF) measurement. The above process is repeated at a plurality of different locations on the wafer to obtain a plurality of GOF measurements for the wafer. Minimum and maximum GOF measurements are determined from the plurality of GOF measurements obtained. If anyone of these GOF measurements are less than a prescribed amount, such as 0.

Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

Abstract: A voltage-controlled oscillator includes at least one voltage-controlled delay element and a reference voltage generator. The voltage-controlled delay element has first and second voltage supply inputs, a control voltage input, a signal input and a signal output. The reference voltage generator has a voltage input coupled to the control voltage input and a voltage output coupled to the first voltage supply input.

Abstract: Serial high speed interconnect devices are integrated with semiconductor devices for simple and reliable communications and control between a plurality of semiconductor devices. The serial high speed interconnect devices transfer the data serially at a rate fast enough to replace large parallel data and address buses that require one conductive path per bit of data. Eliminating large parallel data and address buses allows the integrated circuit containing the semiconductor device to be smaller, simpler and lower in cost. The subsequent reduction in the size of the integrated circuits improves the layout density of electronic systems and reduces crosstalk and other undesirable signal transfer anomalies. The serial high speed interconnection devices are implemented with a low cost serial interface circuit technology that may be easily implemented on a semiconductor die in conjunction with the main circuits.

Abstract: A Reed-Solomon decoder and a decoding algorithm executed by the decoder are disclosed. The decoder includes a syndrome computer and a syndrome processor. The syndrome computer is a pipelined functional unit for computing syndromes from a received codeword and storing erasure location members as flagged by an Erasure Flag signal. The syndrome processor includes a pipelined functional unit and a Chien search circuit for receiving from said syndrome computer the computed syndromes, erasure locations, and number of erasures and computing erasure locator polynomial, modified syndrome polynomial, error locator and error evaluator polynomials, error-erasure locator polynomial, and error value at an error location at each error location found by the Chien search circuit.

Abstract: Affine image transformations are performed in an interleaved manner, whereby coordinate transformations and intensity calculations are alternately performed incrementally on small portions of an image. The pixels are processed in rows such that after coordinates of a first pixel are determined for reference, each pixel in a row, and then pixels in vertically adjacent rows, are processed relative to the coordinates of the previously processed adjacent pixels. After coordinate transformation to produce affine translation, rotation, skew and/or scaling, intermediate metapixels are vertically split and shifted to eliminate holes and overlaps. Intensity values of output metapixels are calculated as being proportional to the sum of scaled portions of the intermediate metapixels which cover the output pixels respectively.

Abstract: A computer implemented method for generating and placing clusters of cells for integrated circuit design includes providing a netlist including cells, and nets of wires interconnecting the cells. A metric is specified for measuring distance between cells as a function of netlist interconnections. A length of a net is the number of cells interconnected by said net minus one, and a distance between two cells is a sum of lengths of nets that provide a shortest path between the cells. A maximum cluster size criterion, such as maximum distance of a cell from the center of a cluster, is specified to provide a desired amount of overlap between clusters. Clusters of cells are generated, each cluster being generated by designating one of the cells as the center, processing the netlist using the metric to determine distances of cells from the center, and assigning cells having progressively increasing distances from the center to the cluster until the maximum cluster size criterion is reached.

Abstract: Disclosed is a method and apparatus for facilitating the decomposition of organometallic compounds such as TEOS in chemical vapor deposition reactors in order to form deposition films. The method generally includes: (1) introducing an organometallic compound and ozone molecules to a chemical vapor deposition reactor; (2) directing ultraviolet radiation into the chemical vapor deposition reactor to increase the rate at which oxygen atoms are formed from the ozone molecules present in the chemical vapor deposition reactor; and (3) decomposing the organometallic compound to form a deposition layer. The organometallic compound decomposes at an accelerated rate due in part to an increased amount of hydroxyl radicals present in the chemical vapor deposition reactor.

Abstract: A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than 900.degree. C., to form oxide in the implanted region of the substrate, and then etching the oxidized substrate to remove a portion of the oxide. The resulting oxidation produces a dual layer of oxide in the substrate. The upper layer is an extremely porous and frothy layer of oxide, while the lower layer is a more dense oxide. The upper porous layer of oxide can be selectively removed from the substrate by a mild etch, leaving the more dense oxide layer in the substrate. Further oxide can then be formed adjacent the dense layer of oxide in the substrate, either by oxide deposition over the dense oxide or by growing further oxide beneath the dense oxide layer.

Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder (outer decoder), thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

Abstract: An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.

Abstract: The port in a packet network switching system that a packet should be associated with is determined by retrieving packet address information for a packet that is to be transmitted. A predetermined number of bits from the packet address information is selected to use a hash key, which is used to compute a table address. The contents of the table at that address are compared with the packet address information. If it matches, the packet is transmitted over the port associated with that particular destination address. If it does not match, the table address is incremented by one, and the contents of the new table location identified by the incremented address are compared with the packet address information. A high speed digital video network apparatus which utilizes the hashing function is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits.

Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design role checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design role checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

Abstract: A system and method implementing a fast wavelet transform by shifting a pair of pixels into a single shift register and using a multimode quadrature mirror filter to eliminate the need of downsampling the filtered signals and to decrease the area required to implement the device on a semiconductor chip.

Abstract: A system for lithographic rastering of an image, defined by an array of pixels, onto an image-accepting substrate that allows irradiation of the total pixel pattern in reduced time. The total image is first divided into a collection of one or more geometrically isolated pixel arrays, with all pixels in an array being connected to each other. Each pixel array is decomposed into a fine region, consisting of all image pixels within P pixels of a boundary of that array, where P is a selected positive integer, such as 1, 2 or 3, and a bulk region consisting of all image pixels in that array that are not part of a fine region. A pixel array may include one or more bulk regions and one or more fine regions. A fine region for a pixel array is further decomposed into a first fine sub-region with pixel width at least equal to P1 pixels, where P1 is a selected integer satisfying 2.ltoreq.P1.ltoreq.P, and a second fine sub-region with pixel width no greater than P1-1 pixels.

Abstract: A digital-to-analog converter (DAC) for converting a multi-bit digital word into a corresponding analog value. The converter divides the digital word into a least significant word portion n.sub.1 and a most significant word portion n.sub.2. The portions overlap in that the weight of the most significant bit (msb) of word portion n.sub.1 is the same as the weight of the least significant bit (lsb) of word portion n.sub.2. The converter detects when the lsb of word portion n.sub.2 changes state, and responsively inverts the state of the msb of word portion n.sub.1. Word portions n.sub.1 and n.sub.2 are then translated into respective analog values which are summed together.

Abstract: A software configuration management and test System for tracking and testing an ASIC design software package includes a library of test programs, an autodetector, an autoverifier, a failure report generator, and a package information logger. The System automatically selects which tests to run on the tools package depending on which portions of which tools have been updated, and then automatically sequences the tools package through the selected tests. By automating the testing process, the System achieves automation, standardization, completeness, and a systematic approach to testing. By greatly reducing test turnaround time, the System also facilitates concurrent engineering.

Abstract: Disclosed is an IC structure providing conductive lines for routing within a semiconductor substrate immediately below the level of the active IC devices. These "buried" conductive lines are insulated from each other by dielectric regions formed as an insulating plane immediately below the active devices and resembling a conventional silicon on insulator (SOI) structure. Within this plane, however, the buried conductive lines provide routes between various active device elements to form some circuit connections such as intracell connections for a gate array. Thus, the buried conductive lines replace some routing from the metallization/dielectric layer stack on top of the active region.