Abstract: A pipelined microprocessor is provided with a queuing stage between an instruction fetch stage and an instruction decode stage to facilitate branch instructions and to receive instructions from the fetch stage when the decode stage is stalled. If a branch is incorrectly anticipated the queuing stage has nonbranch sequential instructions for the decode stage while the fetch stage is restarted at the nonbranch sequential instruction stream.

Abstract: According to the present invention, there is provided a method for fabricating a field effect transistor having reduced hot electron effects. In one embodiment, the method comprises the steps of disposing a gate oxide layer on a semiconductor substrate; disposing a gate material on the gate oxide layer; masking a portion of the gate material; anisotropically etching a gate structure into the gate material such that a trench is formed in the semiconductor substrate; implanting a source structure in the semiconductor substrate, the source structure having a first doping region superjacent a second doping region, the second doping region being lightly doped relative to the first doping region.

Abstract: An electronic system having optical elements in association with photosensitive elements is described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed. Various devices based on such camera arrangements and methods of making same are discussed.

Abstract: A testing apparatus is integrally formed on a microelectronic integrated circuit chip for testing a plurality of memories including parallel outputs having a total of a first number of bits. The apparatus includes an input unit for writing test data into the memories, a parallel output bus having a second number of bits which is smaller than the first number of bits, and an output unit for selectively connecting outputs of the memories to the output bus such that a total number of bits of the selected outputs is not greater than the second number of bits. The outputs of the memories are connected to the output unit in groups, and the output unit is configured to selectively connect the groups of outputs to the output bus in response to respective control signals to read test data out of the memories. Data is applied from the memories to the output unit in bytes.

Abstract: An active load is connected to a power supply terminal of an electronic device such as an integrated circuit. The active load receives a reference voltage that is equal to a normal power supply voltage for application to the terminal, and a source current that is equal to a maximum quiescent power supply current that the device should sink through the terminal. A vector generator applies test signals to the device that cause it to switch between respective operating states. During each operating state, a voltage source that generates the normal power supply voltage is connected to the terminal for a length of time sufficient for the device to attain the respective operating state, and is then removed such that the device is powered only by the active load. After a sufficient length of time has elapsed for the device to achieve a quiescent state, the voltage at the terminal is sensed.

Abstract: A ball bump grid array package includes dies on one surface of a printed wiring board (PWB) and an array of ball bumps on the other surface of the PWB. The die is interconnected with the ball bumps by bond wires, traces on the one surface of the PWB, vias through the PWB and traces on the other surface of the PWB. Various die encapsulation schemes are discussed. The PWB is formed of FR4, BT, teflon or polyimide, or ceramic materials. The die may be connected to the traces on the one surface of the PWB with solder balls, rather than with bond wires. Two or more dies may be disposed on the one surface of the PWB, within the plastic molded body. The ball bumps on the other surface of the PWB may be arranged in a multiple grid pitch array--ball bumps within a central area being on a first pitch, and ball bumps without the central area being on a second pitch which is a multiple of the first pitch.

Abstract: Disclosed is a die structure which allows some or all routing to be performed in an integrated circuit packaging substrate (e.g., a package or circuit board). The packaging substrate acts as one or more interconnect levels. The die and packaging substrate arrangement takes the form of a flip chip design in which multiple solder bumps are formed on an active surface of the die. The active surface is largely or fully "populated" with such solder bumps to allow electrical connection to the packaging substrate at many different sites, depending upon the specific design employed. The solder bumps are electrically connected to various device elements or circuit components on the die itself. In this manner, many different integrated circuit designs may be implemented with the die (in the manner of a gate array) by employing different routing arrangements in the packaging substrate and allowing contact with subsets of the solder pad array.

Abstract: Disclosed herein is a computer capable of transmitting and receiving video and audio signals over an RF bandwidth. The RF bandwidth is allocated among the audio and video signals to allow the audio and video signals to be fitted within the RF bandwidth. The allocation is performed by varying the rates of compression of the audio and video signals. The video is displayed by using fast digital-to-analog converters and a dither technique. An existing computer can be configured for wireless communications by inserting into its backplate a board including a transceiver for transmitting and receiving compressed audio and video signals. The computer's microprocessor is programmed to perform the bandwidth allocation, and can even be programmed to compress and decompress the audio and video signals.

Abstract: A shifter design which is useful in microprocessors is presented. The shifter can perform the operations of a shift right, shift left and shift right arithmetic in which the sign bit of the shifted data word is replicated into the vacated bit positions caused by the shift to the right. The shifter has a rotation count unit, a rotation unit, a mask decoder unit and a logic unit for high-speed operation and occupies a minimal amount of area in an integrated circuit.

Abstract: A method and resulting structure is disclosed for extending or enlarging the effective volumes of one or more source, drain, and/or emitter regions of integrated circuit structures such as an SCR structure and/or an MOS structure designed to protect an integrated circuit structure from damage due to electrostatic discharge (ESD). The additional effective volume allows the SCR and/or MOS protection devices to handle additional energy from an electrostatic discharge applied, for example, to I/O contacts electrically connected to the SCR protection structure. The additional effective volume is obtained, without additional doping or masking steps, by forming individual deep doped regions or wells, beneath one or more heavily doped source, drain, and emitter regions, at the same time and to the same depth and doping concentration as conventional main P wells and/or N wells which are simultaneously formed in the substrate, whereby no additional masks and implanting steps are needed.

Abstract: Process for manufacturing a high interconnection density, fine-line, superconductive printed leadframes using thick-film screen-printing techniques, or other printing techniques. Generally, a superconductive leadframe pattern is printed on a backing substrate. Once the pattern is cured, the backing substrate, or portions thereof can be removed. The backing substrate can be a "fish paper" substrate treated with a release agent, or other substrate material which can be dissolved away, etched away, or otherwise removed. Portions of the backing substrate can be used to provide mechanical integrity for the leadframe. The leadframe fingers can be printed using a superconductive paste or a superconductive precursor paste which is subsequently treated to exhibit superconductivity.

Abstract: A differential-to-CMOS level converter includes a differential-to-CMOS conversion circuit, first and second buffers and a cross-over adjustment circuit. The conversion circuit has first and second differential input terminals and first and second complementary output terminals. The first buffer has a buffer input coupled to the first complementary output and has a buffer output. The second buffer has a buffer input coupled to the second complementary output and has a buffer output. The cross-over adjustment circuit has first and second voltage measurement inputs coupled to the first and second buffer outputs and has first and second offset current outputs coupled to the first and second buffer inputs, respectively.

Abstract: A conformal, substantially uniform thickness layer of photoresist is deposited on a semiconductor wafer by causing photoresist solids to "sediment" out of solution or suspension. Generally, the more conformal the layer, the more uniform the reflectance of the layer and the less variation in underlying feature critical dimension (cd). In order to accommodate possible resulting deviations in photoresist layer thickness causing undesirable reflectance nonuniformities (and cd variations), a top antireflective coating may be applied to the photoresist layer. In the case of a point-by-point lithography process, such as e-beam lithography, the thickness/reflectance variations can be mapped, and exposure doses adjusted accordingly.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: A photolithography optical proximity correction method for mask layouts (e.g., reticle masks) is disclosed. The method includes performing pattern recognition on a layout design to identify locations of feature edges with respect to other feature edges in the layout design. The method further includes obtaining an optical proximity correction for at least one of the feature edges by evaluating one or more non-linear mathematical expressions for optical proximity correction at the location of that edge with respect to other feature edges.

Abstract: An integrated circuit structure vertically isolated electrically from the underlying substrate is formed in/on a single crystal semiconductor substrate, such as a silicon semiconductor wafer, by first implanting the substrate with a sufficient dosage of noble gas atoms to inhibit subsequent recrystallization of the semiconductor lattice in the implanted region during subsequent annealing, resulting in the formation of an isolation layer comprising implanted noble gas atoms enmeshed with semiconductor atoms in the substrate which has sufficient resistivity to act as an isolation layer. The preferred noble gases used to form such isolation layers are neon, argon, krypton, and xenon. When neon atoms are implanted, the minimum dosage should be at least about 6.times.10.sup.15 neon atoms/cm.sup.2 to inhibit subsequent recrystallization of the silicon substrate. When argon atoms are implanted, the minimum dosage should be at least about 2.times.10.sup.15 argon atoms/cm.sup.2.

Abstract: To assemble a flip chip in a package, the back of the flip chip is coated with a heat conductive material and a heat conductive substrate is attached to the heat conductive material. Solder bumps are attached to the front of the flip chip and to a package substrate to mount the flip chip on the package, leaving a space between the flip chip and the package substrate. The space between the flip chip and the package substrate is under filled with a heat conductive media, and the flip chip is encapsulated against the package substrate with a peripheral mold such that at least a portion of the conductive substrate remains exposed. A final package is formed by electrical connectors attached to the package substrate.

Abstract: An n:1 time division multiplexer includes a multiphase clock generator, a data multiplexer, a reference multiplexer, a reference generator and a comparison circuit. The multiphase clock generator has a plurality of select clock outputs with different phases. The data multiplexer has a plurality of data inputs, a plurality of select clock inputs and a data output. The select clock inputs of the data multiplexer are coupled to corresponding select clock outputs. The reference multiplexer has a plurality of reference data inputs, a plurality of select clock inputs and a first reference output. The select clock inputs of the reference multiplexer are coupled to corresponding select clock outputs. The reference generator has a second reference output. The comparison circuit has first and second comparison inputs coupled to the first and second reference outputs, respectively, and has a comparison output coupled to the plurality of select clock outputs.

Abstract: A plurality of macro-arrays are formed on a semiconductor substrate. Each macro-array includes a logic area in which a plurality of interconnectable logic gates are formed, and an Input/Output (I/O) area in which a plurality of I/O devices are formed. I/O terminals are formed outside the I/O area, which enable the logic devices of the macro-arrays to be interconnected with the logic devices of the other macro-arrays via the I/O devices. Alternatively, connections can be made directly to the logic devices. The interconnections are made using a pattern of conductors such that the macro-arrays are linked to form a composite gate array which provides a programmed logical functionality. A number of contiguous macro-arrays which provide the required number of gates are used, with the unused macro-arrays being cut away and discarded.

Abstract: An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon is deposited onto an integrated circuit face at low temperature. A Focused Ion Beam deposition system deposits dopant atoms into the deposited pure silicon in a desired pattern. The dopant atoms are then activated by heat from a focused laser beam which adiabatically anneals the specifically doped areas of the deposited silicon. The resulting annealed doped areas of the silicon have low resistance suitable for circuit conductors. The surrounding undoped silicon reins a high resistance and a good insulator.