Abstract: A method of packaging an integrated circuit. The integrated circuit is connected to a substrate, and a mold is applied to the substrate. The mold and the substrate define a cavity and at least one covered chase, and the integrated circuit is disposed within the cavity. A compound is injected into the cavity through one of the covered chases, underfilling and encapsulating the integrated circuit. In one embodiment the mold is then removed from the substrate. In an alternate embodiment the mold is fixedly applied to the substrate.

Abstract: A differential signal receiver circuit includes a first differential stage receiving input differential signals, a second differential stage receiving shifted differential signals and summing stage summing outputs of the first and second differential stages. Preferably the summing stage is formed by a wired-OR connection between the first and second differential stage outputs. The circuit finds application in digital systems for receiving data transmitted between digital equipment.

Abstract: A process for mounting one or more dies a substrate, such as by ball-bumps. In one embodiment, a thin layer of heat-reflective material, such as gold, is disposed over the surface of the die facing the substrate, to shield the substrate from heat generated by the die. Other embodiments are directed to "pillar" spacers formed on the surface of the die and/or the substrate to control the spacing therebetween. The pillars can be thermally-conductive or thermally non-conductive. Thermally-conductive pillars can be thermally isolated from the die or substrate by an insulating layer. Thermally-conductive pillars can be employed to extract heat from selected areas of a die, into selected lines or areas of the substrate, and the heat on the substrate can then be dissipated by a coolant. Lines on the substrate which are advertently heated by the die can be employed to limit the current of selected circuits on the semiconductor die.

Abstract: A process for designing an integrated circuit chip includes specifying a set of cells, a set of wiring nets for interconnecting the cells, and a set of regions on the chip in which the cells are to be placed. An assignment of the cells of the set to the regions is generated, and the set of cells is randomly divided into a first subset of cells which remain in the assignment, and a second subset of cells which are removed from the assignment. Penalties are computed for assigning the cells of the second subset to the regions respectively, and the cells of the second subset are assigned to the regions such that a total penalty thereof is minimized. The process is repeated iteratively with the size of the second subset being progressively reduced relative to the size of the first subset until an end criterion is reached.

Abstract: A semiconductor processing method forms etch stop layers over semiconductor structures without the need for additional etching, masking, and deposition steps. A refractory metal capable of forming silicides and oxides under standard processing conditions is deposited over the deposition, oxide, and polysilicon layers of a MOS integrated circuit wafer. The coated wafer is first annealed to form refractory metal silicide layers over the unoxidized silicon structures. The coated wafer is then oxidized to convert unreacted refractory metal over the oxidized silicon structures into refractory metal oxide etch stops over these structures.

Abstract: A process where in an interconnect bump is formed on a substrate structure of a flip-chip microelectronic integrated circuit by sputtering a metal base layer on the substrate, and then forming a copper standoff on the base layer. A solder cap is formed on the standoff having a peripheral portion that extends laterally external of the standoff. The peripheral portion of the cap is used as a self-aligned mask for a photolithographic step that results in removing the metal base layer except under the standoff and the cap. The cap has a lower melting point than the standoff. Heat is applied that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt. The peripheral portions of the cap and the base layer that extend laterally external of the standoff cause the melted solder to form into a generally hourglass shape over the standoff due to surface tension.

Abstract: A base cell design is disclosed, which base cell design includes ten transistor base cell design that includes (1) a first group of four n-type transistors; (2) a second group of four p-type transistors; and (3) a third group of two n-type transistors. The transistors in the first and second groups have substantially the same gate widths, while the transistors of the third group have a substantially smaller gate width. Further, the transistors of the first and second groups all have gates that are aligned in parallel with a first axis, and the transistors of the third group all have gates that are aligned in parallel with a second axis that is substantially perpendicular to the first axis. The first and second groups of transistors each contain at least one set of two transistors which are connected in series and share a source/drain region.

Abstract: An apparatus for producing a plasma suitable for semiconductor processing at pressures in the low millitorr range. The apparatus includes a vacuum chamber with a dielectric window, a generally planar coil disposed adjacent the window outside the chamber and coupled to an appropriate power source, and a plasma initiator disposed within the chamber. Once the plasma is initiated, the planar coil sustains the plasma by inductive power coupling. In one embodiment the plasma initiator is a secondary electrode disposed within the chamber and coupled to a second RF power source. In an alternative embodiment both the secondary electrode and a target pedestal are coupled to the secondary RF power source through a power splitter. In an alternative embodiment, the plasma initiator is used to ionize a portion of the process gas and provide a plasma that may then inductively couple with the planar coil.

Abstract: An electronic system utilizing at least one integrated circuit that has reduced drive requirements for the input and output pads of the integrated circuit die. The integrated circuit of the system has an intermediate structure added between the output connection pad and substrate to reduce the amount of electron charge required to charge the output pad capacitance of the integrated circuit to a substantially negligible amount. In addition, an intermediate structure may be added between an input connection pad and substrate of the integrated circuit to reduce the amount of electron charge required to charge the input pad capacitance to a substantially negligible amount.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a later point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: A lid is sealed to an integrated circuit package by a method that uses a spring biased pressure foot that is structurally carried by a secondary loading jig to impose sealant curing load on the lid. The pressure foot is retracted against the spring bias while secondary jig index pins are meshed with corresponding sockets in the fabrication boat that are aligned with the package position on the boat. When the pins and sockets are meshed, the pressure foot is released to apply optimal assembly force at the package center normal of the package lid plane.

Abstract: A circuit for calculating a sum of absolute errors for use in full block search matching in a motion estimation processor is disclosed herein, the circuit being easily implemented and capable of running at 54 Mhz. The circuit accesses search window and reference data from memory and loads the data into rows of laterally interacting processing elements having an architecture capable of fast data processing. A sum of absolute errors between all elements of each row of search data and all elements of each row of reference data is calculated, and the absolute error for all rows of processing elements is totalled. From this total sum of absolute error, the motion vector may be predicted for the next frame.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. An input buffer arrangement includes first and second buffer memories which each have a capacity to store one subframe. The first and second buffer memories are used alternatingly, with one storing a subframe of input data while another subframe is being read out of the other. A third buffer memory, which has a capacity to store at least one subframe, is provided upstream of the first and second buffer memories to prevent the first and second buffer memories from overflowing or underflowing.

Abstract: Method of cooling electronic systems and semiconductor devices as well as an electronic system and a semiconductor device with heat dissipating elements. The method includes the steps of providing an electronic system or a semiconductor device with a heat sink including at least a first element having a generally flat shape with a shoulder projecting from one generally flat surface, and configured to thermally engage similar elements. In one embodiment, a first and a second heat sink element are provided, with one of the first and second elements having a protrusion and the other of the first and second elements defining a depression configured to receive and retain said protrusion. Alternatively, the first and second elements may be bonded together with a thermally conductive adhesive.

Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are non-functional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.

Abstract: A current reference circuit includes a first, current mirror transistor having a gate coupled to a first feedback node, a source coupled to a first supply terminal and a drain forming a first reference node. A second, current mirror transistor has a gate coupled to the first feedback node, a source coupled to the first supply terminal and a drain forming a second reference node. A third transistor has a gate coupled to a second feedback node, a source coupled to a second supply terminal and a drain coupled to the first reference node. A fourth transistor has a gate coupled to the second feedback node, a source coupled to the second supply terminal and a drain coupled to the second reference node. A first operational amplifier has a first input coupled to the first reference node, a second input coupled to a bias node and an output forming the first feedback node.

Abstract: A self-timed phase detector for detecting the phase of an input signal, such as a high speed serial data stream. The self-timed phase detector includes a precharged latch, a phase detector circuit and a data valid gate. The precharged latch has a latch input, a sample clock input and first and second complementary latch outputs. The first and second complementary latch outputs have an active state and a precharged state. The phase detector circuit is coupled to the first latch output and generates a phase signal on a phase output as a function of the phase of the input signal. The data valid gate is coupled to the phase output for passing the phase signal when the latch outputs are in the active state and for blocking the phase signal when the latch outputs are in the precharged state.

Abstract: According to the present invention, there is provided a method for determining glitch power in a logic circuit having a power supply terminal, a first input, a second input, and an output coupled to a capacitive load.

Abstract: A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2.

Abstract: A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell includes the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e.g., polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i.e., programmed) to form substrate level routing between gates of various transistors.