Abstract: Disclosed is a apparatus and method for detecting a cut-off frequency of a pulse signal, the apparatus including an input processor configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor configured to reset the counter at every predetermined (set) period, and a detector configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period.

Abstract: An apparatus for reading data includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, wherein the analog inputs correspond to multiple data tracks on the magnetic storage medium, and wherein the number of analog inputs in the array of analog inputs is greater than the number of data tracks being read, at least one joint equalizer operable to filter the analog inputs to yield an equalized output for each of the data tracks being read, and at least one data detector operable to apply a detection algorithm to the equalized output from the joint equalizer to yield detected values for each of the data tracks being read.

Abstract: A storage system and method for identifying a faulty link the storage system is disclosed. The storage system includes a plurality of target devices and at least one expander configured to communicatively couple a plurality of initiators to the plurality of target devices. Each initiator of the plurality of initiators monitors occurrences of link disruptions independently, wherein upon detecting occurrences of a predetermined number of link disruptions within a predetermined time period, a reporting initiator reports a detection of a faulty link in the multi-initiator topology and requests an arbitrator to identify at least one peer initiator in the multi-initiator topology that shares at least one shared link with the reporting initiator. This reporting initiator and its peer initiators then jointly execute a common diagnostic process to identify the faulty link in the multi-initiator topology.

Abstract: In one embodiment, a segmented digital-to-analog converter (DAC) has two configurations (i.e., sub-DACs) with overlapping operating ranges and a data mapper that maps the digital input signal into two different digital signals, one for each sub-DAC. The currents generated by the sub-DACs are combined and then used to generate the corresponding analog output signal. Because the sub-DACs have overlapping operating ranges, the DAC can be calibrated to account for process variations that result in the actual current ratio between the two sub-DACs being different from the ideal, designed current ratio. Calibration algorithms generate calibration constants that are applied by the data mapper when mapping the digital input signal into the two digital signals respectively applied to the two sub-DACs. In this way, high-precision DACs can be implemented without requiring expensive circuitry to handle undesirable current mismatch resulting from process variations.

Abstract: A system and method for providing Quality of Service (QoS)-based data services in a direct attached storage system including at least one physical drive comprises logically dividing the drive or drives into a plurality of pools implemented according to CRUSH algorithms or other declustered RAID configurations. The plurality of pools are then managed as declustered RAID virtual drives. The system and method further comprises identifying a pool with a performance characteristic and monitoring the pool to detect “hot” data within the pool, which may then be migrated to a pool with a more desirable performance characteristic. The system and method further comprises prioritizing critical operations performed on a pool based on the performance characteristic of the pool.

Abstract: An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics from soft reads of each super-block.

Abstract: Systems and methods presented herein provide for redundancy in I/O caching. In one embodiment, a storage controller includes a first cache operable to receive input/output requests between a host system and a storage device, to compress data of the input/output requests, and to cache the compressed data before writing to the storage device. The storage controller also includes a second cache operable to track chunks of the compressed data in the first cache. When the first cache fails, the second cache is operable to cache the tracked chunks of the compressed data that have not been written to the storage device in a third cache while leaving chunks of data in the second cache that have been written to the storage device.

Abstract: An apparatus having an interface to a plurality of memories and a circuit is disclosed. Each memory generally has a plurality of planes and is nonvolatile. The circuit is configured to (i) generate a plurality of codewords by encoding a plurality of data units, (ii) generate a plurality of slices by parsing the codewords, (iii) generate a plurality of pages by interleaving the slices and (iv) write the pages in parallel into respective ones of the planes.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines may be associated with meta-data indicating one or more of a dirty state and an invalid state. The controller may be connected to the memory and configured to detect an input/output (I/O) operation directed to a file system. The controller may perform a read-fill based on a hint value when there is a read miss in the cache. The hint value may be based on the application access pattern. The hint value may be passed to a caching layer with a corresponding I/O.

Abstract: A method of outputting a positioning pulse by a programmable logic controller (PLC) is provided. The method includes setting up the desired cycle of a pulse to be output; determining a number of needed clocks based on a number of system clocks and a desired frequency according to the desired cycle; determining a total number of needed clocks based on the number of needed clocks and the desired frequency; determining a clock difference based on the number of system clocks and the total number of needed clocks; determining a first number of setup clocks corresponding to a first output pulse in a certain cycle; determining a second number of setup clocks corresponding to pulses except for the first output pulse; and outputting a pulse based on the first number of setup clocks and the second number of setup clocks.

Abstract: There is provided an arc extinguishing unit of a molded case circuit breaker (MCCB) having a structure in which grids and side plates forming an arc chamber are coupled in an inserted manner, facilitating an operation, and intervals of grids are uniformly maintained and a configuration of the grids is not damaged, thus maintaining stable performance and allowing for maintenance.

Abstract: A mobile terminal acquires an item group identifier and an item identifier from a near field communication tag reader which recognizes an item group identification tag and an item identification tag. The mobile terminal acquires item group information related to an item group corresponding to the item group identifier, and extracts information related to an arrangement location of an item corresponding to the item identifier from the item group information. The mobile terminal checks whether or not the item has been correctly arranged based on the arrangement location and an identified location of the item corresponding to the item identifier, so as to display information indicating that the item has been incorrectly arranged.

Abstract: Disclosed is an earth leakage circuit breaker. The earth leakage circuit breaker is capable of determining an earth leakage signal applied thereto with high accuracy, by performing a trip operation by determining noise components included in the earth leakage signal, such as switching noise or harmonics, based on a determination signal generated by tracking the earth leakage signal. The earth leakage circuit breaker is capable of precisely determining whether to perform a trip operation with respect to an earth leakage signal applied thereto. The earth leakage circuit breaker is capable of preventing a malfunction due to a noise signal similar to an earth leakage signal.

Abstract: Methods and systems are provided for enhanced link utilization in attached SCSI (SAS) topologies. A SAS expander may be configured to monitor link utilization within a SAS topology, and may manage connection requests received thereby based on the monitoring of link utilization. The monitoring may comprise determining availability of links for at least one node within the SAS topology with respect to other nodes in the SAS topology. This may be done based on pending connection requests, and/or responses thereto received by the SAS expander. It may also be done based on shared link utilization data. The managing may comprise determining for each received connection request when link unavailability in other nodes within the SAS topology prevents connectivity to a destination node corresponding to the connection request. When this situation occurs, the SAS expander may handle the connection request directly.

Abstract: A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.

Abstract: A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to the memory cells. The voltages are determined in each of a plurality of cases related to inter-cell interference. Step (B) generates a system of equations of a capacitance coupling model in response to the voltages from all of the cases. Step (C) generates one or more parameters in response to the system of equations. The parameters include one or more couplings between a perturbed memory cell and a plurality of neighboring memory cells adjacent to the perturbed memory cell.

Abstract: An on-chip clock controller configured to control cross-domain paths using clock chain signals is disclosed. The on-chip clock controller includes a clock bits module configured to receive a clock chain signal and to output an enable signal based upon the clock chain signal. The on-chip clock controller also includes a clock gating module that is communicatively coupled to the clock bits module. The clock gating module is configured to receive a clock signal and to selectively output either a signal corresponding to the clock signal or a non-transitioning signal based upon the enable signal for operating a state storage module.

Abstract: An integrated interface system for a power-system monitoring and control system is provided. The integrated interface system includes an input and output (I/O) interface unit 220 performing data transmission to and reception from the external data source system; and a data exchange unit exchanging data by using the naming of a fixed electrical bus number for data exchange between a power-system monitoring and control system and the external data source system having a DB different from the power-system monitoring and control system.

Abstract: Data processing systems, circuits and methods are disclosed. As one example, a data processing system is disclosed that includes: a buffer circuit, a data processing circuit, and an erasure window set circuit. The buffer circuit is operable to store a data set as a buffered data set, and the data processing circuit is operable to repeatedly apply a data processing algorithm to the buffered data set. The erasure window set circuit is operable to define a location of the erasure window in relation to the buffered data set.

Abstract: Disclosed herein is a battery protection circuit module device. The battery protection circuit module device includes a charging unit, a battery protection circuit module, and a system. The charging unit includes first and second MOSFET switches, and supplies externally input power to a battery or a system. The battery protection circuit module includes the battery, third and fourth MOSFET switches configured to be selectively turned on and off, a resistor and a capacitor configured to supply the voltage of the battery to the PCM controller as driving power, and the PCM controller configured to control the third and fourth MOSFET switches. The system is operated using the voltage of the battery or externally input voltage. The third and fourth MOSFET switches of the battery protection circuit module are connected via a common drain structure and a common drain terminal is connected to an internal ground.