Abstract: A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.

Abstract: Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

Abstract: Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

Abstract: Apparatus and methods for an improved-efficiency Doherty amplifier are described. The Doherty amplifier may include a two-stage peaking amplifier that transitions from an “off” state to an “on” state later and more rapidly than a single-stage peaking amplifier used in a conventional Doherty amplifier. The improved Doherty amplifier may operate at higher gain values than a conventional Doherty amplifier, with no appreciable reduction in signal bandwidth.

Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Abstract: A mounting clip can be placed and secured over the exterior surfaces of a package of an integrated optical assembly. The mounting clip includes a top panel, end clips that curl and extend down from end edges of the top panel, an interference tab that extends up from the top panel, and cap clips that curl and extend up from the top panel. The mounting clip is dimensioned such that bends in the end clips press and secure against exterior side surfaces of the package of the integrated assembly. Thus, the mounting clip can be secured to the package of the integrated assembly using an interference or friction fit. A cap on a fiber optic cable that extends from the package can be curled around and secured between the interference tab and cap clips of the mounting clip to secure it during surface mounting.

Abstract: A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.

Abstract: Examples of a package for a flange mount device are described. In one example, the package includes a thermally conductive base, a base substrate, and a lid having a cavity. The base substrate includes a through hole and radio frequency (RF) input, RF output, and bias traces that extend to a perimeter of the through hole. The lid includes a cavity and RF input coupling, RF output coupling, and bias coupling traces. A device can be secured to the thermally conductive base, and the lid can be secured to the thermally conductive base, with the base substrate secured between the lid and the thermally conductive base, coupling the traces of the base substrate to the traces of the lid. Other components, such as biasing, blocking, and bypassing components can be easily integrated into the package. Impedance matching and electromagnetic shielding components can also be easily integrated into the package.

Abstract: A voltage controlled oscillator includes a variable capacitance circuit having a plurality of variable capacitance elements, each having a capacitance that is a function of a tuning voltage, two or more oscillator core circuits, each operable over a specified frequency band, and inductive elements connected between the variable capacitance circuit and the oscillator core circuits.

Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Abstract: Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.

Abstract: A digital PLL, which can be a virtual PLL, can condition digital phase information, comprising phase modification requests, for transfer, jitter, and phase-noise filtering of clock information between a clock recovery unit and a clock generation unit associated with phase interpolators. The digital PLL can employ a set of accumulators, proportional and integral filter component, generator component, feedback path between the output and input of the digital PLL, and other digital signal processing components. The proportional and integral filter component can be configurable to set a loop damping factor and a loop bandwidth of the filter, based on respective parameters. Based on the filter output, the generator component can generate output phase information, comprising phase modification requests, that can be transmitted to another phase interpolator(s) associated with a transmitter or other component(s) of the device to facilitate generating a clock for the transmitter or other component(s).

Abstract: A multi-voltage converter is described that includes integrated temperature-protection circuitry. The converter may be used to bias radio-frequency components such as PIN diodes and gallium-nitride devices, and may include integrated bias-sequencing circuitry. Programmable output voltages as high as 30 volts and as low as ?20 volts may be generated.

Abstract: An apparatus includes an input port, an output port, a first bias input, a first shunt PIN diode, a first radio frequency (RF) choke inductor, and a first direct current (DC) blocking capacitor. The input port may be connected to the output port, a first terminal of the first shunt PIN diode, and a first terminal of the first RF choke inductor. A second terminal of the first RF choke inductor is connected to a first terminal of the first DC blocking capacitor and the first bias input. A second terminal of the first shunt PIN diode and a second terminal of the first DC blocking capacitor are connected to a circuit ground potential. A first bias voltage having a magnitude lower than a knee voltage of the first shunt PIN diode is applied at the first bias input.

Abstract: Apparatus and methods for a multiclass, broadband, no-load-modulation power amplifier are described. The power amplifier (500) may include a main amplifier (532) operating in a first amplification class and a plurality of peaking amplifiers (536, 537, 538) operating in a second amplification class. The main amplifier (532) and peaking amplifiers (536, 537, 538) may operate in parallel on portions of signals derived from an input signal to be amplified. The main amplifier (532) may see no modulation of its load impedance between a fully-on state of the power amplifier (all amplifiers amplifying) and a fully backed-off state (peaking amplifiers idle). By avoiding load modulation, the power amplifier (500) can exhibit improved bandwidth and efficiency compared to conventional Doherty amplifiers.

Abstract: Aspects of a symmetric coherent optical mixer are described. In one example, the coherent optical mixer includes a group of symmetric MMI couplers and a group of symmetric bend waveguides optically coupled between the MMI couplers. The group of symmetric MMI couplers can include an input for a local light reference signal, an input for a modulated light signal, and outputs for detection of data from the modulated light signal. The group of symmetric MMI couplers can include four MMI couplers, each of which comprises a 2×2 MMI coupler of symmetric dimension. The group of symmetric bend waveguides can include a symmetric layout of four 90° bend waveguides optically coupled between the four MMI couplers. The coherent optical mixer, which can be implemented as a Silicon Photonics (SiPh) device, provides better performance as a 90° degree optical hybrid than prior mixer devices due to its symmetric layout.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: Apparatus and methods for a no-load-modulation power amplifier are described. No-load-modulation power amplifiers can comprise multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see essentially no modulation of its load between the power amplifier's fully-on and fully backed-off states. The power amplifiers can operate in symmetric and asymmetric modes. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained. Further improvements can be obtained by combining signals from the amplifiers with hybrid couplers.

Abstract: Various aspects provide for a multiplexer for high-speed serial links. For example, a system can include a first stage data path multiplexer circuit and a second stage data path multiplexer circuit. The first stage data path multiplexer circuit comprises a first inverter circuit to select a first data signal from a set of data signals and a second inverter circuit to select a second data signal from the set of data signals. The first inverter circuit comprises a first set of inverters and a first set of transmission gates. The second inverter circuit comprises a second set of inverters and a second set of transmission gates. The second stage data path multiplexer circuit is configured as a third inverter circuit to select the first data signal or the second data signal as an output data signal. The third inverter circuit comprises a third set of inverters and a third set of transmission gates.

Abstract: Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may have cut-outs that allow high-power components to be mounted directly on a heat slug below the laminate. Electrical connections to circuitry on the laminate may be made with wire bonds. The packaging allows more flexible design and tuning of packaged microwave circuitry.