Abstract: A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a III-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.

Abstract: A transimpedance amplifier and photodiode that has a bias voltage node established at a bias voltage and a ground node/plane that connects, over a short distance as compared to the prior art, to a photodiode and a transimpedance amplifier. The photodiode is in a substrate and configured to receive and convert an optical signal to an electrical current. The photodiode has an anode terminal and a cathode terminal which is connected to the bias voltage node. One or more capacitors in or on the substrate and connected between the bias node and the ground node. The transimpedance amplifier has an input connected to the anode terminal of the photodiode and an output that presents a voltage representing the optical signal to an output path. The transimpedance amplifier and the photodiode are both electrically connected in a flip chip configuration and the ground plane creates a coplanar waveguide.

Abstract: System and method of demodulation by adapting constellation values based on statistic distributions of received data symbols. To determine an adapted constellation, an expected ratio of received symbols with values in a certain range is preset based on an expected statistic distribution of data symbols across the multiple constellations. For a set of received symbols, a count ratio of symbols falling in a first range to all the symbols in the set is compared with the expected ratio, where the first range is defined as below a first value. The first value is repeatedly adjusted to adjust the first range until the count ratio equals the expected ratio. The final first value is then designated as the optimal adapted constellation.

Abstract: System and method of timing recovery to achieve sampling phase optimization with aid of equalization adaptation. For equalizer filter, the offset between a current Center of Filter (COF) value and a nominal COF value is used as a measure for a clock phase correction resulted from an adaptive equalization process. A COF may be defined as a function of two selected tap weights or equal to a selected tap weight. The nominal COF value can be dynamically adapted based on the real-time sampling phase error. The tap weights of the equalizer filter are adjusted to decrease the offset, e.g., by interpolating/extrapolating selected tap weights based on the offset. By using sampling phase error as a feedback for COF_nom updating and so for equalization adaptation, the clock delay correction contributed by the adaptive equalization process is advantageously controlled to benefit sampling phase optimization.

Abstract: Apparatus and methods for a modified Doherty amplifier operating at gigahertz frequencies are described. The combining of signals from a main amplifier and a peaking amplifier occur prior to impedance matching of the amplifier's output to a load. An integrated distributed inductor may be used in an impedance inverter to combine the signals. A size of the impedance element can be selected by patterning during manufacture to tune the amplifier and to allow power scaling for the amplifier.

Abstract: A wavelength locker includes first and second waveguides to guide light. The wavelength locker also includes a multimode interference (MMI) coupler having a number of inputs and outputs. First and second inputs of the MMI coupler are coupled to outputs of the first and second waveguides. The MMI coupler merges light from the first and second waveguides to generate an interference pattern of light. The MMI coupler then outputs a plurality of phase shifted versions of the interference pattern. The wavelength locker also includes an interference pattern selector configured to receive signals corresponding, respectively, to light output from the outputs of the MMI coupler. The interference pattern selector is also configured to select one or more outputs of the MMI coupler based on power levels of the interference patterns output from the MMI coupler and a predetermined frequency of a telecommunications frequency grid.

Abstract: High-voltage, gallium-nitride HEMTs are described that are capable of withstanding reverse-bias voltages of at least 900 V and, in some cases, in excess of 2000 V with low reverse-bias leakage current. A HEMT may comprise a lateral geometry having a gate, a thin insulating layer formed beneath the gate, a gate-connected field plate, and a source-connected field plate.

Abstract: A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.

Abstract: An analog-based architecture is used to produce tap spacings in an n-tap UI-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve UI-spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the UI spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

Abstract: A receiver capable of receive and process data signals of multiple baud rates by using an equalizer that is disposed upstream of a decimator. The receiver includes an equalizer coupled to an output of an analog-to-digital converter (ADC), and a decimator couple to the output of the equalizer. The ADC and the equalizer both operate in full rates even in the case of lower data rate, e.g., half or quarter data rate. As the equalizer inherently can inherent remove high frequency noise as well as perform equalization, it practically functions as a low pass filter (LPF). Thereby, there is no need to introduce an extra dedicate LPF upstream of the decimator. This can advantageously and significantly simplify circuitry design and reduce latency.

Abstract: A receiver including an equalizer disposed upstream of a decimator and capable of effectively preventing undesirable interaction between equalization adaptation and the overall timing recovery loop in cases of various data rates. The equalizer operates in a full operation rate even in the case of a lower-than-full data rate, e.g., half or quarter data rate. For input analog signal having 1/M of the full data rate (M>1), M or more Center of Filter (COF) values are determine. Each COF may be derived from a function of a respective set of tap weights and compared with a corresponding nominal COF to obtain a COF offset. The resultant COF offsets are used as indications of clock phase correction caused by equalization adaptation to adjust a set of selected tap weights. The taps selected for adjustment encompass at least M samples to correctly indicate the COF offset associate with one symbol.

Abstract: A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.

Abstract: In one example, a device having integrated package interference isolation includes a ground pad, an integrated circuit device die secured to the ground pad, a substrate secured to the ground pad, at least one a high-frequency, high-power semiconductor device secured to a top mounting surface of the substrate. For electromagnetic isolation, the integrated circuit device die includes a top metal, and the substrate includes a metal via electrically coupled to a metal trace that extends on the top mounting surface of the substrate. The device package also includes a number of ground pad bonding wires that electrically couple the redistribution layer of the integrated circuit device die and the metal trace to the ground pad. The redistribution layer of the integrated circuit device die and the metal trace and via of the substrate help to shield electromagnetic radiation between components in the device package.

Abstract: An apparatus includes a laminate and a lid. The laminate generally includes a dielectric layer between a first conductive layer and a second conductive layer. The first conductive layer may include a probe configured to transfer a radio-frequency signal in a millimeter-wave band. The second conductive layer may be configured to provide a continuous ground plane parallel to the probe and separated from the probe by the dielectric layer. A plurality of channels may be (a) formed into a side of the second conductive layer opposite the dielectric layer, (b) formed to a depth less than a thickness of the second conductive layer, and (c) sized to permit gasses formed while securing the laminate to a substrate to escape from between the laminate and the substrate. The lid may be in contact with the first conductive layer.

Abstract: An apparatus includes a drain node, a plurality of source nodes and a gate node. The drain node may be configured to transfer a drain signal along a first axis from a first port to a second port. The source nodes may be (i) distributed along the first axis and (ii) configured to transfer a plurality of source signals along a second axis from the drain node to a ground node. The gate node may be (i) arranged in parallel to the drain node and (ii) configured to control the source signals in response to a gate voltage. The drain node, the source nodes and the gate node generally form a traveling-wave switch that blocks a slot mode current through the source nodes.

Abstract: The reset signals output to the lanes of a multi-lane coherent transceiver are synchronized by first synchronizing an asynchronous reset signal to a low-speed clock signal to generate and output a plurality of synchronized reset signals to the lanes. Within each lane, a synchronous reset signal is delayed to generate a number of delayed synchronous reset signals, and the logic states of the synchronous reset signal and the delayed synchronous reset signals are captured. Based on the captured logic states in each of the lanes, a lane synchronized reset signal from the delayed synchronous reset signals is selected for use across all of the lanes.

Abstract: An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/fs; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N?1)/fs, and by a delay of 1/fs. The positive sub-DAC and the negative sub-DAC start the conversion at the same time. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of fs.