Abstract: A power amplifier has an amplifier cell with an input terminal receiving an input signal and an output terminal providing an output signal. A bias network is coupled to the output terminal of the amplifier cell to provide a bias signal to the amplifier cell. A shutdown circuit is coupled to the bias network to disable the bias network in response to the input signal. The shutdown circuit has a transistor with a first conduction terminal coupled to the bias network, a second conduction terminal coupled to a power supply terminal. The shutdown circuit further has a first resistor with a first terminal coupled to the input terminal, and a second resistor with a first terminal coupled to a second terminal of the first resistor at a node, and a second terminal coupled to the power supply terminal. The control terminal of the transistor is coupled to the node.

Abstract: A method and system for controlling duty cycle distortion in a signal. The system includes an input configured to receive a square wave input signal and a filter configured to transform the square wave input signal into a signal with sloped transitions. One or more linear buffers introduce duty cycle distortion into the signal based on a duty cycle distortion signal to create a duty cycle distorted signal. One or more output buffers receive and transform the duty cycle distorted signal into a distorted square wave signal. A feedback loop receives the distorted square wave signal and compares it to a duty cycle distortion control signal to generate an error signal, which indicates the difference between the square wave signal and the desired output duty cycle. The error signal is converted to the duty cycle distortion signal and presented to the one or more linear buffers.

Abstract: A single servo control loop for amplifier gain control based on signal power change over time or system to system, having an amplifier configured to receive an input signal on an amplifier input and generate an amplified signal on an amplifier output. The differential signal generator processes the amplified signal to generate differential output signals. The single servo control loop processes the differential output signal to generates one or more gain control signals and one or more current sink control signals. A gain control system receives a gain control signal and, responsive thereto, controls a gain of one or more amplifiers. A current sink receives a current sink control signal and, responsive thereto, draws current away from the amplifier input. Changes in input power ranges generate changes in the integration level of the differential signal outputs which are detected by the control loop, and responsive thereto, the control loop dynamically adjusts the control signals.

Abstract: Techniques for efficient alignment of a semiconductor laser in a Photonic Integrated Circuit (PIC) are disclosed. In some embodiments, a photonic integrated circuit (PIC) may include a semiconductor laser that includes a laser mating surface, and a substrate that includes a substrate mating surface. A shape of the laser mating surface and a shape of the substrate mating surface may be configured to align the semiconductor laser with the substrate in three dimensions.

Abstract: An amplifier system with high gain, compact size, and extended bandwidth is disclosed. The amplifier system includes one or more inputs configured to receive one or more input signals and a pre-driver configured to receive the one or more input signals. The pre-driver may comprise source connected FETs which create a virtual ground and may include inductors which cancel or counter parasitic capacitance of the FETs. The pre-driver amplifies the one or more input signals to create one or more pre-amplified signals, which are provided to a voltage divider network configured to reduce a DC bias voltage of the one or more pre-amplified signals, while maintaining a wide bandwidth range. An amplifier receives and amplifies the output of the voltage divider network to create amplified signals. The amplifier may comprise mirrored FET pairs in a common source configuration and a common gate arrangement.

Abstract: A number of integrated circuits and methods of manufacturing the integrated circuits are described. An integrated circuit can include different semiconductor devices formed from different semiconductor systems in different regions over the same substrate. The integrated circuit can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

Abstract: An optical coupling system for coupling a light source to a photonic integrated circuit (PIC) comprises a multimode coupler configured to receive an input optical signal of a first mode. The multimode coupler triggers one or more higher-order modes from the input optical signal of the first mode. The optical coupling system also includes a mode de-multiplexer and an optical combiner. The mode de-multiplexer transfers the input optical signal of the first mode and one or more optical signals of the triggered one or more higher-order modes to respective output optical signals of the first mode. The optical combiner combines the respective output optical signals to produce a single output signal of the first mode.

Abstract: A hybrid diode silicon on insulator front end module and related method are provided. The front end module includes a transmit branch that includes a transmit circuit and a receive branch that includes a receive circuit. The receive circuit includes a low noise amplifier, a pin diode including an anode and a cathode; and a switch. The anode of the pin diode is operatively connected to an antenna switch port and an input voltage source. The cathode of the pin diode is operatively connected to a cathode of the switch. Turning on the switch facilitates a drainage of residual electrical current at the pin diode.

Abstract: A semiconductor device has a substrate and a first semiconductor layer with a high resistivity, such as an epitaxial layer with a resistivity in the range of 3000-5000 ohms/cm2, formed over the substrate. A second semiconductor layer is formed at least partially in the first semiconductor layer. A capacitor is formed at least partially over the first semiconductor layer. The capacitor has a plurality of trenches extending through the first semiconductor layer and into the substrate, and a first insulating layer formed in the trench. The trenches can be parallel, serpentine, or other geometric shape. The capacitor also has a second insulating layer formed over the first insulating layer, and a polysilicon layer formed over the second insulating layer. A conductive layer is formed over the capacitor. The first semiconductor layer with high resistivity provides a vertical path to discharge high voltage events incident on the capacitor.

Abstract: A cable equalizer configured as part of a cable comprising a first stage, a second stage, and a third stage. The first stage comprises a first stage bias current circuit configured to generate a bias current and a pre-emphasis module configured to introduce pre-emphasis into a received signal to counter the effects of signal amplification. Also part of the first stage is a bias voltage circuit configured to provide a bias voltage to the first stage. The second stage comprises a buffer configured impedance match the first stage. The third stage comprises a third stage bias current circuit configured to generate a bias current and a tank equalizer circuit configured to perform frequency specific equalization on a second stage signal. An amplifier is configured to amplify the second stage signal to create an amplified signal, which is output from the cable equalizer by an output driver.

Abstract: A multi-level optical signal is sampled to generate an eye diagram. The signal can be adjusted when eyes in the eye diagram have different heights. More specifically, a first value is determined, and the height of a first eye is adjusted using the first value. The first value is multiplied by a stored factor to produce a second value, and the height of a second eye is adjusted using the second value, and so on for other eyes. As a result, eye heights are the same. Similarly, optical power levels of the signal can be adjusted when the levels are not equally spaced. As a result, the optical power levels are equally spaced.

Abstract: A laser structure may include a substrate, an active region arranged on the substrate, and a waveguide arranged on the active region. The waveguide may include a first surface and a second surface that join to form a first angle relative to the active region. A material may be deposited on the first surface and the second surface of the waveguide.

Abstract: Active bias circuits for integrated devices are described. In one example, an active bias circuit includes a voltage control element to establish a control voltage, an active bias device to provide a power bias responsive to the control voltage, and a compensation circuit connected to the active bias device. The compensation circuit can be configured to set output impedance and compensate for parasitic capacitance of the active bias device. In another embodiment, the voltage control element can be omitted, and a control voltage can be relied upon to directly control the power bias output provided by the active bias device. The active bias circuit can be used to power a driver of an integrated optical transmitter, in one example, among other possible applications.

Abstract: Various integrated circuits formed using gallium nitride and other materials are described. In one example, an integrated circuit includes a first integrated device formed over a first semiconductor structure in a first region of the integrated circuit, a second integrated device formed over a second semiconductor structure in a second region of the integrated circuit, and a passive component formed over a third region of the integrated circuit, between the first region and the second region. The third region comprises an insulating material, which can be glass in some cases. Further, the passive component can be formed over the glass in the third region. The integrated circuit is designed to avoid electromagnetic coupling between the passive component, during operation of the integrated circuit, and interfacial parasitic conductive layers existing in the first and second semiconductor structures, to improve performance.

Abstract: A number of monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a monolithic multi-throw diode switch have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm.

Abstract: An optical module configured to electrically connect to a host. A linear equalizer performs equalization on a host equalized signal to create a module equalized signal, and a driver configured to present the module equalized signal from the linear equalizer to an optical conversion device at a magnitude suitable for the optical conversion device. An optical conversion device receives the module equalized signal from the driver, converts the module equalized signal to an optical signal, and transmit the optical signal over an optical channel. Also part of the optical module is an interface which communicates supplemental equalizer settings to the host. A memory stores the supplemental equalizer settings which reflect the optical modules effect on a signal passing through the optical module. A controller oversees communication of the supplemental equalizer settings to the host such that the host uses the supplemental equalizer settings to modify host equalizer settings.

Abstract: An arrayed waveguide grating device includes an input coupler configured to receive a light signal and split the light signal into a plurality of output light signals. The device also includes a plurality of waveguides optically connected to the input coupler, each waveguide having a plurality of waveguide portions having respective sensitivities to variance in one or more parameters associated with operating of the optical arrayed grating device. Lengths of the respective portions are determined such that each waveguide applies a respective phase shift to the output light signal that propagates through the waveguide and the plurality of waveguides have at least substantially same change in phase shift with respective changes in the one or more parameters associated with operation of the device. An output coupler is optically connected to the plurality of waveguides to map respective light signals output from the plurality of waveguides to respective focal positions.

Abstract: A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

Abstract: A dc coupled amplifier includes a pre-driver, and amplifier and a bias control circuit. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to create one or more pre-amplified signals. The amplifier has cascode configured transistors configured to receive and amplify the one or more pre-amplified signals to create one or more amplified signals, the amplifier further having an output driver termination element. The bias control circuit is connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias current from the output driver termination element of the amplifier, wherein the pre-driver, the amplifier and the bias control circuit are all formed on a same die.

Abstract: A serializer clock delay optimization system comprising a multiplexer configured to receive two or more low-rate data signals and a multiplexer control signal. The multiplexer generates a full-rate data signal by combining the two or more low-rate data signals such that the multiplexer control signal determines sampling time of the low-rate data signals. A data monitor monitors and evaluates the full-rate data signal to generate a quality value representing the quality of the full-rate data signal. The quality of the full-rate data signal is based on the accuracy of the sampling time of the low-rate data signals. A delay controller processes the quality value to generate a delay control signal or value. A delay receives a clock signal and the delay control signal or value. Responsive to the delay control signal or value, the delay modifies the timing of the clock signal to create the multiplexer control signal.