Abstract: Various aspects provide for a digitally programmable analog duty-cycle correction circuit. For example, a system includes a duty-cycle correction circuit and a duty-cycle distortion detector circuit. The duty-cycle correction circuit adjusts a clock associated with the transmitter. The duty-cycle distortion detector circuit facilitates digital control of a duty-cycle of the clock associated with the duty-cycle correction circuit based on duty-cycle distortion error associated with output of the transmitter.

Abstract: Apparatus and methods for a multiclass, broadband, no-load-modulation power amplifier are described. The power amplifier (500) may include a main amplifier (532) operating in a first amplification class and a plurality of peaking amplifiers (536, 537, 538) operating in a second amplification class. The main amplifier (532) and peaking amplifiers (536, 537, 538) may operate in parallel on portions of signals derived from an input signal to be amplified. The main amplifier (532) may see no modulation of its load impedance between a fully-on state of the power amplifier (all amplifiers amplifying) and a fully backed-off state (peaking amplifiers idle). By avoiding load modulation, the power amplifier (500) can exhibit improved bandwidth and efficiency compared to conventional Doherty amplifiers.

Abstract: A configurable phased array tile is disclosed including an aperture assembly having a plurality of aperture assembly connectors, a backplane assembly having a plurality of backplane assembly connectors, and a plurality of vertical transmit cards mounted to a corresponding first plurality of aperture assembly connectors and a corresponding first plurality of backplane assembly connectors. The plurality of vertical transmit cards each include a plurality of transmit channels including at least one high power transmit amplifier for powering at least one radiating element mounted to the aperture assembly.

Abstract: A diode semiconductor structure is described. In one example, a diode device includes a substrate, a layer of first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact.

Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Abstract: Semiconductor electro-optical modulators which receives an input optical signal and provides a modulated output optical signal based on an input electrical signal are disclosed. The semiconductor electro-optical modulator may comprise at least one electrical transmission line adapted to carry the input electrical signal and a semiconductor electro-optical phase shifter waveguide electrically coupled to the at least one electrical transmission line. An optical path length of the semiconductor electro-optical phase shifter waveguide between a modulation begin plane of the semiconductor electro-optical modulator and a modulation end plane of the semiconductor electro-optical modulator may be greater than an electrical path length of the electrical transmission line between the modulation begin plane of the semiconductor electro-optical modulator and the modulation end plane of the semiconductor electro-optical modulator.

Abstract: Apparatus and methods for an improved-efficiency Doherty amplifier are described. The Doherty amplifier may include a two-stage peaking amplifier that transitions from an “off” state to an “on” state later and more rapidly than a single-stage peaking amplifier used in a conventional Doherty amplifier. The improved Doherty amplifier may operate at higher gain values than a conventional Doherty amplifier, with no appreciable reduction in signal bandwidth.

Abstract: Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

Abstract: Apparatus and methods for a modified Doherty amplifier operating at gigahertz frequencies are described. The combining of signals from a main amplifier and a peaking amplifier occur prior to impedance matching of the amplifier's output to a load. An integrated distributed inductor may be used in an impedance inverter to combine the signals. A size of the impedance element can be selected by patterning during manufacture to tune the amplifier and to allow power scaling for the amplifier.

Abstract: A transimpedance amplifier and photodiode that has a bias voltage node established at a bias voltage and a ground node/plane that connects, over a short distance as compared to the prior art, to a photodiode and a transimpedance amplifier. The photodiode is in a substrate and configured to receive and convert an optical signal to an electrical current. The photodiode has an anode terminal and a cathode terminal which is connected to the bias voltage node. One or more capacitors in or on the substrate and connected between the bias node and the ground node. The transimpedance amplifier has an input connected to the anode terminal of the photodiode and an output that presents a voltage representing the optical signal to an output path. The transimpedance amplifier and the photodiode are both electrically connected in a flip chip configuration and the ground plane creates a coplanar waveguide.

Abstract: A method and apparatus for processing a signal to generate equalizer codes, which are used to control equalization of the signal, that comprises processing the signal to identify the eyes of the signal, and for each eye, calculating an eye height and calculating a noise value. For each eye, squaring the eye height to generate an eye height product and dividing the eye height product by the noise value to generate a Q2 value. Using the calculated Q2 values optimizing, through adaptation, the equalizer codes. Calculating the noise values may include calculating an ISI value for each band of the signal and then calculating the eye height for each eye as the difference between the adjacent upper average value and the adjacent lower average value. Then, for each eye, calculating a noise value by summing the ISI value for the band above the eye and the band below the eye.

Abstract: An improved method and system for locating a slicer threshold and phase is disclosed. A two-dimensional field of coordinates is defined using phase versus eye monitor magnitude. At each coordinate, the number of samples above the eye monitor magnitude are counted. Dividing by the total number of samples considered yields a ratio between 0 and 1. Each eye 0, 1, 2 (bottom, middle, top in a PAM4 system) has an ideal ratio (75%, 50%, 25%) assuming a balanced distribution of PAM4 levels. The rating (third dimension) at each coordinate is calculated to be (0.25?abs.value (actual_ratio?ideal_ratio)) limited to positive results only. The resulting ratings are summed over phase. The eye center is calculated using weighted average of the sums. The eye center is compared to the calibrated target to determine which way to move the slicer threshold.

Abstract: Apparatus and methods for a no-load-modulation power amplifier are described. No-load-modulation power amplifiers can comprise multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see essentially no modulation of its load between the power amplifier's fully-on and fully backed-off states. The power amplifiers can operate in symmetric and asymmetric modes. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained. Further improvements can be obtained by combining signals from the amplifiers with hybrid couplers.

Abstract: A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a III-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.

Abstract: Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

Abstract: A method and system for reducing power supply noise comprising receiving a primary data stream at a data rate. The primary data stream comprises a stream of bits having logical values of either zero or one. Then, splitting the primary data stream to create a first group of lower rate data streams and a second group of lower rate data streams. Processing the second group of lower rate data streams to invert the logic values of the bits of the lower rate data streams to create processed lower rate data streams. The first group of lower rate data streams are combined with the processed lower rate data streams to create a complementary data stream. Then, processing the primary data stream and the complementary data stream concurrently with a data processing system, the concurrent processing reducing noise on the power supply.

Abstract: Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

Abstract: A system for controlling equalization applied to a received signal comprising an equalizer configured to equalize on a received signal to generate an equalized signal, and a clock recovery module configured to recover a clock signal from the equalized signal or the received signal. A clock adjustment system is configured to receive the clock signal, and at least one control signal, to create a sampling clock signal. A filter is configured to filter the equalized signal to create a filtered signal. A sampling unit samples the filtered signal or the equalized signal such that the output of the sampling unit is provided to a controller. The controller is configured to receive and process the output of the sampling unit to generate a boost signal, and the controller is further configured to provide the boost signal to the equalizer to control the amount of equalization performed by the equalizer.

Abstract: Extrinsic structure that is formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. Extrinsic structure is described that can reduce gate leakage current in transistors by over four orders of magnitude.

Abstract: A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a diode limiter semiconductor structure have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. The thin intrinsic region PIN diode can be optimized for low level turn on and flat leakage, and the thick intrinsic region PIN diode can be optimized for low capacitance, good isolation, and high incident power levels. This configuration is not limited to two stage solutions, as additional stages can be used for higher incident power handling.