Abstract: A printing system comprises a memory configured to store image data representing an image. The printing system comprises a processor configured to perform a first digital halftone process on a first portion of the image and a second digital halftone process on a second portion of the image.

Abstract: A system for processing subscriber line data signals uses a coprocessor to receive signals in a pre-determined order from a plurality of line interface cards. The coprocessor uses the pre-determined order to sort the data signals by tone and process all received signals on the same tone at the same time. Because all signals on a tone, or those on a tone with known crosstalk issues, are processed together, the signal improvement is better than prior art methods. When not used, the coprocessor may be replaced with a loop-back circuit to reduce cost when crosstalk is not a significant issue.

Abstract: A network apparatus comprises a plurality of ports, and a forwarding engine coupled to the plurality of ports. The forwarding engine is configured to transfer data units received via at least some of the plurality of ports to one or more appropriate ports in the plurality of ports. The forwarding engine comprises a content addressable memory (CAM) device to store a plurality of data patterns organized in a plurality of groups, wherein the CAM device is configured to, responsive to input data, output in a single cycle a plurality of match indications corresponding to the plurality of groups. The forwarding engine also comprises a logic device coupled to the CAM device and configured to generate an action value based on the plurality of match indications, wherein the action value indicates an action to be taken by the forwarding engine.

Abstract: A media access control (MAC) processor includes a programmable controller and a memory coupled to the programmable controller to store machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A hardware processor is coupled to the programmable controller. The hardware processor includes a processing engine configured to implement MAC functions on the data received by the communication device. The hardware processor additionally includes a context memory coupled to the processing engine to store state information of the processing engine corresponding to one or more contexts, and context switch logic coupled to the processing to determine when the processing engine should switch contexts.

Abstract: An apparatus (such as a printer) including a combination engine controller circuit board having a integrated circuit (IC) chip configured to process (format) incoming data as well as to control the operations of the apparatus is disclosed. The IC chip is adapted to receive and process data as well as to control the operations of the apparatus. For this reason, the IC chip is referred to as a combined controller IC.

Abstract: A disk drive system-on-chip (SOC) includes a read-channel module and a processor. The read-channel module reads data, includes a first error-correcting module for correcting errors in the data, corrects errors in a first portion of the data using the first error-correcting module, and is unable to correct errors in a second portion of the data using the first error-correcting module. The processor includes a processor core and processor memory, receives the second portion of the data in the processor memory, and corrects errors in the second portion of the data using a second error-correcting module that is different than the first error-correcting module.

Abstract: The disclosed technology provides a system and a method for adaptive MPEG noise reduction. In particular, the disclosed technology provides a system and a method for reducing blocking artifacts and mosquito noise in an MPEG video signal. An overall MPEG noise detector may be used to determine the presence of noise in one or more frames of a video signal. When a sufficient amount of noise is detected in the one or more frames of the video signal, portions of the video signal that contain noise may be located and filtered to reduce the amount of noise present in the video signal.

Abstract: Laser write parameters in an optical drive are calibrated. A parameter range for the write parameters is set based on a recordable medium, and a number of test runs are recorded on the recordable medium while varying the write parameters. Write performance characteristics over the test runs are measured. Based on the measured performance characteristics, actual write parameters are selected for use in writing actual data.

Abstract: An amplifier biasing circuit that reduces gain variation in short channel amplifiers, an amplifier biasing circuit that produces a constant Gm biasing signal for short channel amplifiers, and a multistage amplifier that advantageously incorporates embodiment of both types of amplifier biasing circuits are described. Both amplifier biasing circuit approaches use an operational amplifier to equalize internal bias circuit voltages. The constant Gm biasing circuit produces a Gm of 1/R, where R is the value of a trim resistor value. The biasing circuit that reduces gain variation produces a Gm of approximately 1/R, where R is the value of a trim resistor value, however, the biasing circuit is configurable to adjust the bias circuit Gm to mitigate the impact of a wide range of circuit specific characteristics and a wide range of changes in the operational environment in which the circuit can used, such as changes in temperature.

Abstract: An RF receiver image rejection scheme. The RF is received and mixed in two quadrature channels allowing separation of the undesired image portion within the RF signal from the desired portion. The two channels can be summed to allow the image portions to cancel out and form a signal which is predominantly based on the desired portion. Another sum of the two channels can also be made to provide a signal which is primarily based on the image portion. Since there are some components of the image portion even in the compensated desired signal, that signal indicative of the image portion is used to compensate for that undesired portion.

Abstract: Devices, systems, and techniques for equalization include, in at least some implementations, a first equalizer that produces first equalized data responsive to input data by reducing a total power of both noise and inter symbol interference components of the input data, a first detector that produces first output data responsive to the first equalized data, a second equalizer that produces second equalized data responsive to the first output data by maximizing bit error rate performance, and a second detector that produces second output data responsive to the second equalized data.

Abstract: An indication of modulation constrained capacity of a multiple input multiple output (MIMO) communication channel is determined. The indication of modulation constrained capacity corresponds to one modulation scheme from a plurality of modulation schemes. The indication of modulation constrained capacity corresponding to the one modulation scheme is compared to a threshold corresponding to the one modulation scheme. A modulation scheme is selected from the plurality of modulation schemes based on the comparison of the indication of modulation constrained capacity to the threshold.

Abstract: A method for communication includes receiving signals at a receiver from one or more sources, including a target signal transmitted by a given transmitter. A channel response is estimated from the given transmitter to the receiver, and a filter response is computed by taking a sum of an autocorrelation of the received signals with an adaptive noise factor, and applying the sum to the estimated channel response. The filter response is applied to the received signals in order to recover the target signal.

Abstract: Circuits and methods for utilizing multiple programmable memory using one-time programmable (OTP) memory in a fan controller. The fan controller generally includes a plurality of OTP memories, each capable of being programmed once and only once; a state machine configured to enable writing updated parameter information to an available OTP memory and to provide a control signal indicating a next OTP memory to which next received data are to be written, and read logic coupled to the plurality of OTP memories, the read logic configured to read an output from a most recently programmed OTP memory. The method generally includes receiving updated parameter information to be stored in the memory, programming one of a plurality of one-time programmable (OTP) memories with the updated parameter information, indicating an availability of a next OTP memory, and reading an output from a most recently programmed OTP memory.

Abstract: Systems and methods for encoding user information and decoding signal vectors using fractional encoding/decoding and set partitioning. A fractional encoder can select a coset for transmitting or storing user information based on one or more deterministic bits and on encoded user information. The deterministic bits limit the encoder to using only a subset of the available signal vectors in a modulation scheme. A fractional decoder can receive a signal vector, and can find at least two nearest neighbors in each dimension. The fractional decoder can form a set of potential signal vectors using only the at least two nearest neighbors. The decoder may determine which of these potential signal vectors are valid within the fractional signaling scheme, and can decode the received signal vector based on the valid potential signal vectors.

Abstract: A system including a read module, a clock generator module, and a write module. The read module generates read signals in response to reading servo spirals from a magnetic medium of a hard disk drive. The clock generator module generates a spiral clock based on the read signals, and generates, based on the spiral clock, (i) a first write clock and (ii) a second write clock. The spiral clock has a first frequency, the first write clock has a second frequency, and the second write clock has a third frequency. The write module is configured to (i) write a first servo wedge on a first zone of the magnetic medium of the hard disk drive based on the first write clock, and (ii) write a second servo wedge on a second zone of the magnetic medium of the hard disk drive based on the second write clock.

Abstract: A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first locations associated with the first index. Indexing the translation table with a second index of the virtual address corresponding to a second memory region size by querying the translation table at second locations associated with the second index. The translation table includes translations for mapping address tags of the virtual address to physical addresses. The first index is different than the second index, and the first memory region size is different than the second memory region size.

Abstract: A communication system including a plurality of communication devices configured to operate according to a plurality of communication clock signals, respectively, wherein the plurality of communication clock signals are based on a common reference clock signal. The communication system further includes a phase-locked loop configured to generate an output signal in response to the common reference clock signal, wherein the output signal is in phase lock with the common reference clock signal; a signal division controller configured to generate a divider reset signal in response to a binary select signal; and a divider configured to generate one of the plurality of communication clock signals by performing frequency division of the output signal, wherein the divider reset signal controls a start time of the frequency division.

Abstract: Secure memory controlled access is described. In embodiment(s), memory stores encrypted data and the memory includes a secure memory partition to store cryptographically sensitive data utilized to control access to the encrypted data stored on the memory. Controller firmware can access the encrypted data stored on the memory, but is precluded from access to the secure memory partition and the cryptographically sensitive data. Secure firmware can access the cryptographically sensitive data stored on the secure memory partition to control access by the controller firmware to the encrypted data stored on the memory.

Abstract: The present invention relates to a processor (1) and a method for a processor comprising processing means (2), the method comprising the steps of—admitting a data packet (D1, D2, D3) to the processing means (2) based at least partly on a value (CS1) of a first credit, parameter and a first limit (L1S1) of the first credit parameter,—decreasing the value (CS1) of the first credit parameter if the data packet (D1, D2, D3) is admitted to the processing means (2), and—increasing the value (CS1) of the first credit parameter, in dependence on a value (CS2) of a second credit parameter, based on which a data packet (D1, D2, D3) is admitted to the processing means (2).