Abstract: A cryptographic device comprises a first pipeline stage, a pipeline register, and a second pipeline stage. The first pipeline stage comprises a first byte substitution module that performs mathematical operations on a received byte and outputs an intermediate value based on the mathematical operations. The pipeline register stores the intermediate value. The second pipeline stage comprises a second byte substitution module and a column mixing module. The second byte substitution module generates a replacement byte corresponding to the received byte based on mathematical operations performed on the stored intermediate value. The column mixing module transforms groups of four bytes of a plurality of replacement bytes including the replacement byte.

Abstract: A self learning roaming optimization approach allows a wireless client device to build signal strength maps that store wireless network access point signal strengths at locations along paths traveled by the wireless client device within an operational environment. The signal strengths collected at locations along a path may be analyzed to determine a recommended wireless network access point at the respective locations to achieve a reliable wireless network connection along the mapped path. The stored recommendations may take into account changes in wireless network access point signal strengths, e.g. due to obstructions and/or electromagnetic shields that may block portions of a wireless network access point signal at subsequent locations along the mapped path.

Abstract: A method of decoding a signal transmitted via a multiple input multiple output (MIMO) communication channel includes obtaining a first set of parameters associated with a first plurality of transmitters transmitting a plurality of intended streams, obtaining a second set of parameters associated with an interference source, receiving a plurality of streams including the plurality of intended streams; and decoding the plurality of intended streams using the first set of parameters and the second set of parameters.

Abstract: A decoder memory system comprises a first memory comprising at least a portion of a parity check matrix H. A second memory receives the portion from the first memory and that is associated with a previous decoding iteration. A third memory communicates with the first memory, receives the parity check matrix H and is associated with a current decoding iteration. A fourth memory comprises likelihood ratios. A control module generates a LDPC decoded signal based on the parity check matrix H, the previous decoded iteration and the likelihood ratios.

Abstract: Methods, apparatuses, and systems implementing analog techniques to decode signals extracted from servo wedges of computer-readable storage media. A digital signal representing a repeatable runout (RRO) signal included in an analog signal of a computer-readable storage medium is obtained. The RRO signal includes a preamble that represents a magnitude of the RRO signal, and data. The digital signal includes a digital representation of the preamble. An estimate of the magnitude of the RRO signal is determined based on the digital representation. The estimate is compared with a specified level to generate an error signal based on a difference between the two. The provision of the error signal, for application to a subsequent RRO signal of the computer-readable storage medium, is delayed. The RRO signal is amplified prior to being represented as the digital signal to match a value established to decode the RRO signal.

Abstract: In one embodiment the present invention includes a voltage regulator circuit comprising a voltage to current converter. The voltage to current converter is coupled to provide a current to maintain an output voltage under changing load conditions. A transconductance of the voltage to current converter is independent of the output current and therefore improves stability for the voltage regulator across load conditions.

Abstract: Described herein are methods and apparatuses for testing an integrated circuit chip including a thermal diode. According to various embodiments, a method for testing an integrated circuit chip including a thermal diode may comprise performing a test operation on the integrated circuit chip, and during the test operation, detecting a signal representative of a temperature sensed by a thermal diode embedded in the integrated circuit chip. Other embodiments may be described and claimed.

Abstract: A system and method for providing a fast recovery for voltage bias applied to an MR sensor, when a voltage is applied to the MR sensor very quickly while the MR sensor transitions from an idle or sleep state to an active state includes an apparatus and method for adjusting the voltage and range applied to the MR sensor. The apparatus includes a circuit having a current biasing circuit for supplying a current bias to a transducer, a voltage biasing circuit configured to supply a voltage bias to a transducer, and a charge pump for maintaining the current bias and the voltage bias at the maximum range so that the voltage at the transducer is maximized.

Abstract: Aspects of the disclosure can provide a method to optimize optical recording. The method can include recording a pre-defined pattern on an optical medium according to a first write strategy, measuring edge timings corresponding to the pre-defined pattern recorded on the optical medium, determining a second write strategy including at least timing modifications to the first write strategy. The timing modifications can be determined based on means and variances of the measured edge timings, edge timing means and variances targets for desired edge timings, and edge timing sensitivities to the timing modifications.

Abstract: Particular embodiments generally relate to detecting an operating mode of a flyback converter. In one embodiment, a voltage of a flyback converter is measured. A waveform for the voltage includes a first rate of change when the flyback converter is in a first mode of operation and a second rate of change when the flyback converter is in a second mode of operation. The presence of the first rate of change or the second rate of change is detected based on the waveform. The first mode of operation or the second mode of operation is determined depending on whether the first rate of change or the second rate of change is detected.

Abstract: A method comprising applying a first voltage to a first transistor to create a defect in the first transistor, wherein (i) the first voltage is greater than a maximum operational voltage of the first transistor and (ii) the maximum operational voltage does not cause a defect in the first transistor when applied to the first transistor. The method further includes determining whether the first transistor has been programmed, including (i) measuring a first current through the first transistor, (ii) measuring a second current through a second transistor, and (iii) comparing the measured first current to the measured second current, wherein a difference between the measured first current and the measured second current indicates that the first transistor has been programmed.

Abstract: A method for detecting a security breach in a network comprises at one of a plurality of transceivers each having a different media access control address, receiving a signal from an access point, the signal representing one or more packets of data, determining a source media access control address for each of the packets, and alerting the access point when the source media access control address of one of the packets is the media access control address of the transceiver.

Abstract: A method is provided for controlling access to a wireless communications medium. The method includes: sampling RF activity on the medium; autocorrelating samples to produce a first value indicative of autocorrelation computed with a first delay substantially matching periodicity of a signal of interest and to produce a second value indicative of autocorrelation computed with a second delay different from the first delay; monitoring the first value to determine whether the first value is possibly indicative of the signal of interest; monitoring the second value to determine whether the second value is indicative of an interferer signal; and preventing transmission of an RF transmit signal on the medium in response to the first value indicating that activity on the medium includes the signal of interest when the second value indicates that activity on the medium does not include an interferer signal.

Abstract: A read head circuit includes a read element configured to read data stored magnetically on a platter. The read element includes a first terminal and a second terminal. A normally-ON transistor includes a first terminal, a second terminal and a control terminal. The first terminal is directly connected to the first terminal of the read element. A second terminal is directly connected to the second terminal of the read element. Responsive to the control terminal being powered, the normally-ON transistor provides an open circuit between the first terminal of the read element and the second terminal of the read element. Responsive to the control terminal not being powered, the normally-ON transistor is configured to short the first terminal of the read element to the second terminal of the read element.

Abstract: Systems and methods for enhancing soft decoders and detectors on asymmetric channels are provided. The methods include acquiring log-likelihood ratios (LLRS) for error-correction code (ECC) encoded data symbols, selecting a quality measure function and a quality threshold based on the LLRs, applying the selected quality measure function to the LLRs to obtain quality measures, comparing the quality measures to the selected quality threshold, and updating the LLRs for selected ECC encoded data symbols based on the comparisons. The updating may occur by multiplying the LLRs for the selected ECC encoded data symbols by a selected scaling factor.

Abstract: A phase-locked loop that supports a large frequency drift capability, yet maintains a low Kvco, and does not introduce noise or discontinuities in the frequency of the generated phase-locked loop output signal. The phase-locked loop may include a VCO with an LC tank circuit, the capacitance of which may be adjusted in incremental units. By gradually adjusting a control signal applied to a selected VCO LC tank circuit frequency adjustment control line, e.g., in a continuous ramped function, or time-averaged ramped function, from LOW-to-HIGH or from HIGH-to-LOW, over a period of time that is greater than the response time of the phase-locked loop, a frequency range supported by the VCO may be shifted to either a higher frequency range or a lower frequency range, as needed, to accommodate environmentally induced frequency drift in the VCO, without introducing noise or discontinuities in the frequency of the generated phase-locked loop output signal.

Abstract: A transmit data rate adaptation method in a multiple-in-multiple-out (MIMO) system with a first transceiver and a second transceiver. The first transceiver transmits signals to the second transceiver. The second transceiver analyzes channel quality of the received signals and uses link adaptation to generate a shortlist of transmit modes to send back to the first transceiver. The first transceiver cycles through the shortlist of transmit modes to find an optimum transmit mode.

Abstract: Devices, systems, methods, and other embodiments associated with an interface for solid state memory are described. In one embodiment, an apparatus is implemented with two or more input ports for receiving two or more different streams of disk drive commands. The apparatus is further implemented with an interface configured to aggregate the two or more different streams of disk drive commands into at least one aggregated command. The interface is configured to translate the at least one aggregated command into at least one solid state memory command for accessing solid state memory. The apparatus comprises a memory port to communicate the at least one solid state memory command to be performed on the solid state memory.

Abstract: A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability.

Abstract: Various embodiments provide improved mesh networks with properties that address various shortcomings of current mesh network implementations. At least some embodiments are directed to improving operations of mesh networks in connection with battery powered devices and address concerns associated with latency issues due to power save nodes as well as load balancing. Yet other embodiments address route cache timeouts, reduce route discovery overhead, perform proactive route maintenance based on a node's battery, and provide a straightforward battery-aware process based sleep protocol.