Patents Assigned to Marvell International
  • Enhanced host sleep for WLAN devices
    Patent number: 8170624
    Abstract: In a method and apparatus for controlling operation of a wireless device, a host assembly of the wireless device enters into a handshaking procedure with firmware of the wireless device to initiate entry into or exit from a host sleep mode. Before such entry or exit, the handshaking procedure may require the host assembly to send an initiation handshake signal to the firmware, and require the firmware to send a confirmation handshake signal back to the host assembly. Entry or exit may be delayed until after the confirmation signal is received. The confirmation signal may vary depending on the handshaking configuration and activation data, and the confirmation signal may vary depending on whether the wireless device is in a power save mode or not.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: May 1, 2012
    Assignee: Marvell International Ltd.
    Inventors: Frank Huang, James Kang-Wuu Jan, Robert Lee, Sandesh Goel, Bing Zhao, Yao Chen, Chen Fan
  • Hybrid defect detection for recording channels
    Patent number: 8164846
    Abstract: Methods, systems and computer program products for performing hybrid defect detection are disclosed. A hybrid defect detection mechanism may be used to detect various classes of defects (e.g., long and shallow defects, and short and deep defects) while reducing the probability of a miss or false alarm. In some implementations, the hybrid defect detection mechanism may utilize a defect detector that includes one or more defect sub-detectors. Each defect sub-detector may be associated with an individual threshold and sliding window length to enhance the hybrid defect detection process that maximizes the detection of a specific type or class of defects.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Yu-Yao Chang, Michael Madden, Zining Wu
  • Method and apparatus for detecting land pre-pits
    Patent number: 8164993
    Abstract: Aspects of the disclosure provide a method for detecting land pre-pits. The method can adaptively adjust a threshold for detecting the land pre-pits in order to improve the correctness of detecting. The method for detecting land pre-pits can include extracting a land pre-pit data stream from a reading signal based on a land pre-pit threshold, the reading signal corresponding to land pre-pits of an optical medium, comparing the land pre-pit data stream with format information of the optical medium to obtain an error signal, and adjusting the land pre-pit threshold based on the error signal.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventor: Jingfeng Liu
  • Circuits and methods for amplifying signals
    Patent number: 8164383
    Abstract: In one embodiment, the present disclosure includes an amplifier comprising first and second output stages. The first output stage receives first power supply voltages and the second output stage receives second power supply voltages greater than the first power supply voltages. A switching stage configures the output stages to provide a first current to an amplifier output node from the first output stage when a magnitude of a voltage on the output node is below a first value, provide a second current to the output node from the second output stage when the magnitude of the voltage on the output node is above a second value greater than the first value, and provide a third current to the output node from both the first output stage and the second output stage when the magnitude of the voltage on the output node is between the first value and the second value.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Alex Lollio, Giacomino Bollati, Rinaldo Castello
  • Regulating an operating condition of an integrated circuit to compensate for a manufacturing variation
    Patent number: 8164390
    Abstract: An integrated circuit has operational circuitry to perform an operation. An operational regulator regulates an operating condition of the operational circuitry. The operational regulator has a sample clock to generate a sample clock signal. The sample clock signal correlates to a manufacturing variation of the electronic circuitry. The operational regulator also includes a configurator to evaluate the sample clock signal and generate a configuration signal according to the evaluation. A controller is provided to receive the configuration signal and control an operating condition of the operational circuitry according to the configuration signal.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: April 24, 2012
    Assignees: Marvell International Ltd., Marvell Israel (MISL) Ltd.
    Inventors: Randall D. Briggs, Eran Maor, Walter Lee McNall, William B. Weiser, Haggai Telem
  • Method and apparatus for filtering
    Patent number: 8165555
    Abstract: Aspects of the disclosure can provide a second order low pass filter. The second order low pass filter can work in current domain, and have high linearity for in-band signals and out-of-band signals. The second order low pass filter can include a MOS transistor having a gate terminal, a current input terminal and a current output terminal, a first capacitor coupled between the current input terminal and a ground connection and a second capacitor coupled between the gate terminal and the current input terminal.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Fernando De Bernardinis, Rinaldo Castello
  • Device, system and method for multi-profile wireless communication
    Patent number: 8165628
    Abstract: Briefly, some embodiments of the invention may provide devices, systems and methods for multi-profile wireless communication. For example, a wireless communication module may include first and second ports, and may be able to selectably operate in either a first mode of operation, in which said first port is used as an input port for incoming signals and said second port is used as an output port for outgoing signals, or a second mode of operation, in which said second port is used as an input port for incoming signals and said first port is used as an output port for outgoing signals.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: April 24, 2012
    Assignee: Marvell International, Ltd.
    Inventor: David Sinai
  • Floating frame timing circuits for network devices
    Patent number: 8166216
    Abstract: A networking device includes a network port configured to receive a message from a remote networking device. The network port includes a detector configured to detect reception of the message. A queue controller is configured to integrate a timestamp with the message to generate a modified message. An ingress timer is configured to generate the timestamp based on an arrival time of the message at the network port.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventor: Raghu Kondapalli
  • Method and apparatus for asymmetry correction in magnetic recording channels
    Patent number: 8164845
    Abstract: A circuit for compensating asymmetry in a waveform of an input signal using a piecewise approximation of a saturation curve, the circuit including a first circuit configured to output a first compensation for a first section of the saturation curve using a first function and a second circuit configured to output a second compensation for a second section of the saturation curve using a second function. The second function is different than the first function. The first compensation and the second compensation provide the piecewise approximation of a region of the saturation curve. The region includes at least the first second and the second section.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Sriharsha Annadore, Mahendra Singh
  • Methods for forming a single cap via in pad of substrate
    Patent number: 8161635
    Abstract: Novel methods are provided that results in the formation of single-cap VIPs in a substrate are described herein. As a result, fine pitch trace patterns may be formed on the substrate. The methods may include initially providing a substrate having a first and a second side, the first side being opposite of the second side. A via may then be constructed in the substrate, the via being formed within a via hole that extends from the first side to the second side of the substrate, the formed via having a first end located at the first side of the substrate, and a second end opposite the first end located at the second side of the substrate. A selective deposition may be performed of a conductive material on the second end of the via to form a conductive pad directly on the via on the second side of the substrate without depositing the conductive material onto the first side of the substrate.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventor: Chien Te Chen
  • System and method for generating a frequency rich spectrum in a data stream
    Patent number: 8165176
    Abstract: A system and method for generating a frequency rich spectrum in a data stream is disclosed. A network interface comprises a substitutor module, a symbol replacement module, and an encoder module. The substitutor module replaces idle streams in a first data stream with alignment symbols, boundary symbols and disposable symbols to generate a second data stream. The symbol replacement module receives the second data stream, generates random data, and replaces one or more of the disposable symbols in the second data stream with the random data in order to generate a third data stream. The encoder module encodes the third data stream.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: William Lo, Tsungtang Wang, Xing Wu
  • Calculating soft information from a multi-level modulation signal
    Patent number: 8166379
    Abstract: Apparatus and methods are provided for calculating soft information in a multi-level modulation scheme using one or more nearest neighbors. The nearest neighbors correspond to signal points in a signal constellation set nearest to the value of a received signal. The nearest neighbors of a received signal can be found by using a second symbol-to-signal point mapping for the signal constellation set that is different from the mapping actually used by the signal modulator. The second symbol mapping can be used to simplify the discover of nearest neighbors. Once the nearest neighbors are found in the second symbol mapping, the nearest symbols can be translated back into the actual symbol mapping using, for example, table lookup. The nearest neighbors in the actual symbol mapping can then be used to compute soft information in the form of, for example, log-likelihood ratios (LLRs).
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Zining Wu, Nedeljko Varnica, Xueshi Yang
  • System and method for reading and writing data using storage controllers
    Patent number: 8166217
    Abstract: A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Theodore C. White, William W. Dennin, Angel G. Perozo
  • Efficient RAID ECC controller for RAID systems
    Patent number: 8166370
    Abstract: A Redundant Array of Inexpensive Disks (RAID) controller comprises a RAID error correction code (ECC) encoder module that receives data for storage and that generates code words for data drives and one or more parity drives, which have physical locations. The code words are generated based on the data and a cyclic code generator polynomial. Logical locations correspond to index positions in the cyclic code generator polynomial. A mapping module maps the physical locations of the data and parity drives to the logical locations. The mapping module adds a new data drive to an unused one of the logical locations. A difference generating module generates a difference code word based on the new data drive. The RAID ECC encoder module encodes the difference code word and adds the encoded difference code word to an original code word generated before the new data drive is added.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Heng Tang, Zining Wu, Gregory Burd, Pantas Sutardja
  • Aysmmetric sense-amp flip-flop
    Patent number: 8164363
    Abstract: An Asymmetric Sense-Amp Flip-Flop (ASAFF) is disclosed that may achieve zero setup time and short clock-to-Q delays. The ASAFF captures input data at a clock transition by setting values of a first node and a second node in a manner that is input data value dependent. If the input data is at the first input data value, the first node is set and held at a first storage value after a first delay, and the second node is set and held at a second storage value after a second delay, and if the input data is at a second input data value, the first node is set and held at a third storage value after a third delay, and the second node is set and held at a fourth storage value, after a fourth delay. This internal-path dependent difference in delay enables ASAFF to achieve zero setup time.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventor: Jason Su
  • Unfolded decision-directed loop, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in decision-directed loops
    Patent number: 8165247
    Abstract: Unfolded adaptive/decision-directed loops and correction circuits therefor, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in an adaptive and/or decision-directed loop. Disclosed embodiments advantageously reduce effects of loop latency, improve the accuracy of corrections in an adaptive loop, and minimize overhead and delays associated with such improvements.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Michael Madden, Zining Wu
  • Address decoder
    Patent number: 8164972
    Abstract: An address decoder that includes a plurality of predecoders configured to (i) receive and logically combine a clock signal and address signals and (ii) generate addresses and complementary addresses. At least one of the plurality of precoders includes a first logic gate configured to receive the clock signal and one of the address signals, and a second logic gate configured to receive the clock signal and an output of the first logic gate. The address decoder further includes a decoder configured to generate a decoder output based on the addresses and complementary addresses.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventor: Jason T. Su
  • Nested transimpendance amplifier
    Patent number: 8159293
    Abstract: A nested transimpedance amplifier circuit including a first power source, a second power source, a charge pump module and a transimpedance amplifier. The first power source is at a first voltage. The second power source is at a second voltage. The second voltage is different than the first voltage. The charge pump module (i) receives the first voltage and the second voltage and (ii) generates a third voltage based on the first voltage and the second voltage. The first transimpedance amplifier includes an input, an output and a first operational amplifier. The input of the first transimpedance amplifier receives an input voltage. The output of the first transimpedance amplifier outputs an output voltage. The first operational amplifier receives the third voltage. The first transimpedance amplifier generates the output voltage based on the third voltage and the input voltage.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: April 17, 2012
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Smart printer cartridge
    Patent number: 8161199
    Abstract: A system and method are disclosed for modifying the capabilities and functions of a printer after it is manufactured. A consumable/replaceable printer cartridge includes a storage device having updated and/or additional printer function data and other data for use by the printer control circuitry to execute printer functions and other types of functions. In addition, when the printer cartridge is installed in the printer the storage device may be utilized by the printer control circuitry as expanded memory for use in executing the updated and/or additional printer functions and other types of functions.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: April 17, 2012
    Assignee: Marvell International Ltd.
    Inventors: William B. Weiser, Mark D. Montierth
  • Tap connections for circuits with leakage suppression capability
    Patent number: RE43326
    Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Lawrence T. Clark, Vikas R. Amrelia, Raphael A. Soetan, Eric J. Hoffman, Tuan X. Do