Abstract: Apparatuses, systems, and techniques to establish a redundant communication pathway to a management network. In at least one embodiment, the redundant communication pathway is established by creating a virtual interface using a network device, and using the virtual interface to communicate with the management network via a management port of a second network device, and a connection between a first data port of the network device and a second data port of the second network device.

Abstract: A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of cells of memory, one or more ports read data from the shared buffer and write data to the shared buffer, and a controller circuit selectively enables and disables cells of memory of the shared buffer based on an amount of data stored in the shared buffer. Power consumption of the shared buffer is in proportion to a number of enabled cells of memory.

Abstract: Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.

Abstract: Various embodiments of the present disclosure provide for generating and managing a digital ledger access system and its associated objects. An example method is configured for securing objects in a digital ledger of objects by identifying an object from amongst a plurality of objects in the digital ledger of objects and generating a quantum token for attachment with the object. The method includes deriving one or more classical public keys associated with the quantum token and determining an attempt to access the object. The method provides access to the object in response to a validation of the classical public key based on the quantum token, and the method precludes access to the object in response to an invalidation of the classical public key based on the quantum token.

Abstract: In one embodiment, a secure challenge-response method includes requesting respective token challenges from devices, receiving the respective token challenges from the devices, providing the respective token challenges to a signing server, receiving from the signing server a signature of the respective token challenges signed with a private key of the signing server, and providing to a given device of the devices a request to perform an operation, the request including the signature and the respective token challenges.

Abstract: In one embodiment, a data communication device includes a network interface controller to process packets received from at least one of a host device for sending over a network, and at least one remote device over the network, at least one processor to execute computer instructions to receive a configuration, and extract filtering rules from the configuration, and at least one hardware accelerator to receive the filtering rules from the at least one processor, and filter the packets based on the rules so that some of the packets are dropped and some of the packets are forwarded to the at least one processor to send data based on the forwarded packets to another device.

Abstract: A network element includes a transmit-queue for transmitting packets from at least two sources, each source having a predefined priority level, to a headroom buffer in a peer network element. Flow-control circuitry receives from the peer network element signaling that indicates a number of credits for transmitting packets to the peer network element, manages a current number of credits available for transmission from the transmit-queue, responsive to the signaling, selects a threshold priority based on the current number of credits for the transmit-queue; and transmits packets associated with data sources of the transmit-queue that are higher in priority than the threshold priority, and refrain from transmitting other packets associated with the transmit-queue.

Abstract: A datacenter environment having a plurality of servers, leaf switches, and spine switches is presented. A transceiver module facilitates reliable data transmission across network layers. The transceiver module includes a first optical module to facilitate data transmission between a server and a leaf switch, and a second optical module to facilitate data transmission between the leaf switch and a spine switch. An adapter operatively coupled to both optical modules manages data flow under different configurations. In a first configuration, the adapter receives first data from the server via the first optical module and second data from the leaf switch via the second optical module. Upon detecting an operational failure in the first optical module, the adapter terminates reception of second data from the leaf switch and switches to a second configuration, in which it redirects the first data from the server through the second optical module.

Abstract: A first and a second flange assembly configured for facilitating uniform and laminar flow in a system are provided. The first flange assembly includes a first flange body configured to introduce a gas into a chamber. The first flange assembly includes a plurality of outlet tubes disposed on an interior surface of the first flange body and a plurality of inlet tubes disposed on an exterior surface of the first flange body and in fluid communication with the plurality of outlet tubes. The second flange assembly includes a second flange body configured to remove the gas from the chamber. The second flange assembly includes a plurality of through holes extending from an interior surface to an exterior surface of the second flange body and a plurality of exit tubes extending from the exterior surface of the second flange body and in fluid communication with the plurality of through holes.

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

Abstract: A method and system for analyzing Vertical-Cavity Surface-Emitting Lasers (VCSELs) on a wafer are provided. An illustrative method of is provided that includes: applying a stimulus to each of the plurality of VCSELs on the wafer; measuring, for each of the plurality of VCSELs, two or more VCSEL parameters responsive to the stimulus; correlating the measured two or more VCSEL parameters to define a value of a common performance characteristic; and identifying clusters of VCSELs having similar values of the common performance characteristic. The clusters of VCSELs may be determined to collectively meet or not meet an optical performance requirement defined for the VCSELs on the wafer.

Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

Abstract: In one embodiment, a clock synchronization system includes clock circuitry to maintain a clock running at a clock frequency, a clock controller, and a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to apply the clock update commands to the clock, store a holdover frequency command to maintain the clock during a failure of the clock update commands, apply the holdover frequency command to the clock responsively to detecting the failure.

Abstract: A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i) a pattern of offsets to be accessed in the memory and (ii) a memory key representing a memory space to be accessed using the pattern, and to transfer the data in accordance with the request.

Abstract: A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.

Abstract: A method includes providing a library of hardware-agnostic packet-processing functions. A functional hardware-agnostic specification of a packet-processing pipeline is received from a user. The specification is defined in terms of one or more of the packet-processing functions drawn from the library. A hardware-specific design of the packet-processing pipeline, which is suited to given hardware, is derived from the specification.

Abstract: A network node includes a network adapter and a host. The network adapter is coupled to a communication network. The host includes a processor running a client process and a communication stack, and is configured to receive packets from the communication network, and classify the received packets into respective flows that are associated with respective chunks in a receive buffer, to distribute payloads of the received packets among the chunks so that payloads of packets classified to a given flow are stored in a given chunk assigned to the given flow, and to notify the communication stack of the payloads in the given chunk, for transferring the payloads in the given chunk to the client process.

Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

Abstract: In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the timer is activated responsively to a quantity of the multiple missing data packets.