Patents Assigned to Mellanox Technologies Ltd.
  • Patent number: 12284783
    Abstract: A device may include: a frame having an interior; an electronic component; a heat conducting body in thermal contact with the electronic component; a conduit containing a liquid coolant, the conduit being coupled to the heat conducting body to deliver the liquid coolant to and from the heat conducting body; and a pump positioned within the interior of the frame, the pump being removably insertable into the interior of the frame and being removably couplable to the conduit to circulate the liquid coolant through the conduit.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: April 22, 2025
    Assignee: Mellanox Technologies Ltd.
    Inventors: Oren Weltsch, Rom Becker, Shay Zaretsky, Ayal Shabtay, Beeri Halachmi, Yuval Blayer, Kfir Katz, Yuval Dagan, Bar Noyman
  • Patent number: 12284100
    Abstract: In one embodiment, data communication device includes a network interface to receive first packets over a network from another network device via a switch, which includes a buffer associated with a variable buffer delay, and packet processing circuitry to compute respective measures of delay over the network to the other network device over time responsively to the received first packets, find a minimum measure of delay over the network to the other network device responsively to at least some of the computed respective measures of delay, estimate a current measure of buffer delay of the buffer responsively to the found minimum measure of delay and a current one of the computed respective measures of delay, set a packet processing parameter responsively to the estimated current measure of buffer delay, and process second packets responsively to the set packet processing parameter.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: April 22, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventor: Yuval Shpigelman
  • Patent number: 12284162
    Abstract: A network interface controller includes processing circuitry configured to pair with a local root of trust of a host device connected to the network interface controller and provide a key to an encryption device of the host device that enables the encryption device to encrypt data of one or more host device applications using the key. The encrypted data are stored in host device memory. The processing circuitry is configured to share the key with a remote endpoint and forward the encrypted data from the host device memory to the remote endpoint.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 22, 2025
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dimitrios Syrivelis, Dotan David Levi, Paraskevas Bakopoulos, Ioannis (Giannis) Patronas, Elad Mentovich
  • Patent number: 12284120
    Abstract: A network adapter includes a host interface, a network interface, a packet processor, and a telemetry handler. The host interface is to communicate with a host. The network interface is to send packets to a network. The packet processor is to process the packets prior to sending the packets to the network. The telemetry handler is to receive from the host, over the host interface, an indication specifying a flow or application, to mark one or more packets associated with the flow or application with a specified identifier in response to the indication, and to send the marked packets using the packet processor to the network via the network interface.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: April 22, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Ortal Bashan, Yaki Tebeka
  • Patent number: 12282775
    Abstract: A network device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the network device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The instruction processor includes architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and the match-action circuitry is to write into the architectural registers information for performing the programmable action.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: April 22, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Ariel Shahar, Avi Urman, Omri Kahalon, Uria Basher, Doron Haim, Sagi Farjun
  • Patent number: 12284115
    Abstract: Multipathing for session-based remote direct memory access (SRDMA) may be used for congestion management. A given SRDMA session group may be associated with multiple SRDMA sessions, each having its own unique 5-tuple. A queue pair (QP) associated with the SRDMA session group may provide a packet for transmission using the SRDMA session group. The SRDMA session group may enable the packet to be transmitted using any of the associated SRDMA sessions. Congestion levels for each of the SRDMA sessions may be monitored and weighted. Therefore, when a packet is received, an SRDMA session may be selected based, at least, on the weight to enable routing of packets to reduce latency and improve overall system efficiency.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: April 22, 2025
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Adi Merav Horowitz, Omri Kahalon, Rabia Loulou, Gal Shalom, Aviad Yehezkel, Liel Yonatan Maman, Liran Liss
  • Patent number: 12278662
    Abstract: Systems, computer program products, and methods are described herein for network discovery, port identification, and/or identifying fiber link failures in an optical network, in accordance with an embodiment of the invention. The present invention may be configured to sequentially connect each port of an optical switch to a network port of a server and generate, based on information associated with network devices connected to the ports, a network map. The network map may identify which network devices are connected to which ports of the optical switch and may permit dynamic port mapping for network installation, upgrades, repairs, and/or the like. The present invention may also be configured to determine a fiber link in which a failure occurred and reconfigure the optical switch to allow communication between an optical time-domain reflectometer and the fiber link to test the fiber link.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: April 15, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Paraskevas Bakopoulos, Konstantinos Tokas, Ioannis (Giannis) Patronas, Nikolaos Argyris, Dimitrios Syrivelis, Dimitrios Kalavrouziotis, Elad Mentovich, Eitan Zahavi, Louis Bennie Capps, Jr., Prethvi Ramesh Kashinkunti, Julie Irene Marcelle Bernauer
  • Patent number: 12278304
    Abstract: Various embodiments of improved PIN-type photodiodes are provided. In an example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a second absorbing layer disposed between the first absorbing layer and the n-type contact. The first absorbing layer is characterized by a first absorption coefficient and the second absorbing layer is characterized by a second absorption coefficient. The second absorption coefficient is greater than the first absorption coefficient. In another example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a non-absorbing accelerating layer disposed between absorbing layers and non-absorbing drift layer and the n-type contact.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 15, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yuri Berk, Vladimir Iakovlev, Tamir Sharkaz, Elad Mentovich, Matan Galanty, Itshak Kalifa, Paraskevas Bakopoulos
  • Patent number: 12277068
    Abstract: A peripheral device includes a bus interface and an Address Translation Service (ATS) controller. The bus interface is to communicate over a peripheral bus. The ATS controller is to communicate over the peripheral bus, including sending address translation requests and receiving address translations in response to the address translation requests, to cache at least some of the address translations in one or more Address Translation Caches (ATCs), to estimate one or more statistical properties of the received address translations, and to configure the one or more ATCs based on the one or more statistical properties.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: April 15, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Gal Shalom, Daniel Marcovitch, Ran Avraham Koren, Amir Sharaffy, Shay Aisman, Ariel Shahar
  • Patent number: 12278755
    Abstract: A switch, communication system, and method are provided. In one example, a communication system is described that includes a plurality of communication nodes and a switch that interconnects and facilitates a transmission of packets between the plurality of communication nodes. The communication system may be configured such that the packets are transmitted between the plurality of communication nodes by draining a demand matrix.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: April 15, 2025
    Assignee: Mellanox Technologies, LTD.
    Inventors: Gal Mendelson, Jose Yallouz
  • Patent number: 12273281
    Abstract: An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress domains and one or more egress domains. The crossbar circuit includes sub-crossbar domains. An ingress control circuit associated with the one or more ingress domains may distribute packet data of the one or more packets to the sub-crossbar domains. An egress control circuit of the apparatus receives data bits associated with the packet data from egresses associated with the plurality of sub-crossbar domains. The egress control circuit may reorder or refrain from reordering the data bits based on an attribute associated with the distribution of the packet data.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: April 8, 2025
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Idan Matari, Matisyahu Meier Goldmeier, George Elias, Ofir Klara Altshul, Itamar Rabenstein, Noam Michaelis, Eyal Srebro
  • Patent number: 12273380
    Abstract: A device receives a packet from a local network. The packet may be directed toward a cloud computing resource. The device determines that the packet is associated with a new packet flow. In response to determining that the packet is associated with the new packet flow, the device provides one or more packets from the new packet flow to a machine learning model for packet inspection. The device receives an output from the machine learning model and routes the new packet flow based on the output received from the machine learning model. The output indicates whether or not the new packet flow is associated with a network attack.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 8, 2025
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan Finkelshtein, Alexander Bilkovskii, Roni Bar Yanai, Juan Jose Vegas Olmos
  • Publication number: 20250112872
    Abstract: A system and method for establishing connections in a computer network supporting a remote direct memory access (RDMA) protocol, may include: generating a plurality of dummy queue pairs, each generated with dummy parameter values; and upon receiving a request to establish a connection from a first computer node in the computer network, turning one of the dummy queue pairs into a functional queue pair by changing a subgroup of the dummy parameter values to true parameter values.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Mellanox Technologies, Ltd.
    Inventors: Yuval AVNERY, Charlie MUBARIKI
  • Patent number: 12265497
    Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: April 1, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Daniel Marcovitch, Richard Graham
  • Patent number: 12261881
    Abstract: Apparatuses, systems, and techniques for classifying a candidate uniform resource locator (URL) as malicious using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service to protect one or more computer programs executed by the host device. The security service extracts a set of features from data stored in the physical memory, the data being words in a candidate URL and numeric features of a URL structure of the candidate URL. The security service classifies, using the ML detection system, the candidate URL as malicious or benign using the set of features. The security service outputs an indication of a malicious URL responsive to the candidate URL being classified as malicious.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: March 25, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Vadim Gechman, Nir Rosen, Haim Elisha, Bartley Richardson, Rachel Allen, Ahmad Saleh, Rami Ailabouni, Thanh Nguyen
  • Patent number: 12260007
    Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is to communicate with an NVM. The processor is to store in the NVM at least a Type-Length-Value (TLV) record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least a validity indicator of the TLV record, to read the TLV record from the NVM, and to invalidate the TLV record by modifying the validity indicator stored in the non-encrypted fields, without decryption of any of the encrypted fields.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: March 25, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Yuval Itkin, Nir Eilam
  • Patent number: 12259832
    Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: March 25, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Tzahi Oved, Achiad Shochat, Liran Liss, Noam Bloch, Aviv Heller, Idan Burstein, Ariel Shahar, Peter Paneah
  • Patent number: 12259963
    Abstract: A confidential computing (CC) apparatus includes a CPU and a peripheral device. The CPU is to run a hypervisor that hosts one or more Trusted Virtual Machines (TVMs). The peripheral device is coupled to the CPU and to an external memory. The CPU includes a TVM-Monitor (TVMM), to perform management operations on the one or more TVMs, to track memory space that is allocated by the hypervisor to the peripheral device in the external memory, to monitor memory-access requests issued by the hypervisor to the memory space allocated to the peripheral device in the external memory, and to permit or deny the memory-access requests, according to a criterion.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: March 25, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Boris Pismenny, Miriam Menes, Ahmad Atamli, Ilan Pardo, Ariel Shahar, Uria Basher
  • Patent number: 12262502
    Abstract: Devices, apparatuses, systems, and methods are provided for improved thermal management in networking computing devices. An example thermal management apparatus includes a housing defining a first end and a second end opposite the first end. The apparatus further includes an electronic component supported within the housing, such as a GPU. The apparatus includes a primary inlet that receives a primary airflow having a first temperature and a secondary inlet that receives a secondary airflow having a second temperature where the second temperature is different than the first temperature. The primary airflow and the secondary airflow are collectively configured to dissipate heat generated by the electronic component.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: March 25, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Ran Hasson Ruso, Tahir Cader, Elad Mentovich, Susheela Narasimhan
  • Patent number: 12255734
    Abstract: In one embodiment, a system includes a network interface controller including a device interface to connect to a processing device and receive a time synchronization marker message from an application running on the processing device, a network interface to send packets over a network, and packet processing circuitry to process the time synchronization marker message for sending via the network interface over the network to a slave clock device, generate a time synchronization follow-up message including a timestamp indicative of when the synchronization marker message egressed the network interface, and process the time synchronization follow-up message for sending via the network interface over the network to the slave clock device.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: March 18, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Wojciech Wasko, Dotan David Levi, Avi Urman, Natan Manevich