Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

Abstract: Apparatuses, systems, and techniques for classifying a candidate uniform resource locator (URL) as malicious using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service to protect one or more computer programs executed by the host device. The security service extracts a set of features from data stored in the physical memory, the data being words in a candidate URL and numeric features of a URL structure of the candidate URL. The security service classifies, using the ML detection system, the candidate URL as malicious or benign using the set of features. The security service outputs an indication of a malicious URL responsive to the candidate URL being classified as malicious.

Abstract: Devices, apparatuses, systems, and methods are provided for improved thermal management in networking computing devices. An example thermal management apparatus includes a housing defining a first end and a second end opposite the first end. The apparatus further includes an electronic component supported within the housing, such as a GPU. The apparatus includes a primary inlet that receives a primary airflow having a first temperature and a secondary inlet that receives a secondary airflow having a second temperature where the second temperature is different than the first temperature. The primary airflow and the secondary airflow are collectively configured to dissipate heat generated by the electronic component.

Abstract: A confidential computing (CC) apparatus includes a CPU and a peripheral device. The CPU is to run a hypervisor that hosts one or more Trusted Virtual Machines (TVMs). The peripheral device is coupled to the CPU and to an external memory. The CPU includes a TVM-Monitor (TVMM), to perform management operations on the one or more TVMs, to track memory space that is allocated by the hypervisor to the peripheral device in the external memory, to monitor memory-access requests issued by the hypervisor to the memory space allocated to the peripheral device in the external memory, and to permit or deny the memory-access requests, according to a criterion.

Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is to communicate with an NVM. The processor is to store in the NVM at least a Type-Length-Value (TLV) record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least a validity indicator of the TLV record, to read the TLV record from the NVM, and to invalidate the TLV record by modifying the validity indicator stored in the non-encrypted fields, without decryption of any of the encrypted fields.

Abstract: In one embodiment, a processing device includes a memory to store a plurality of memory pages having corresponding physical memory addresses in the memory, store an active multilevel page table (MPT) mapping virtual to physical memory addresses for corresponding allocated memory pages stored in the memory, and store a floating MPT at least partially mapping virtual to physical memory addresses for corresponding spare memory pages stored in the memory, the floating and active MPT using a common mapping scheme, and a processor to receive a request to add a virtual to physical address mapping for more memory pages of the plurality of memory pages to the active MPT, and in response to receiving the request, adjoin at least part of the floating MPT to the active MPT so that the active MPT provides the virtual to physical address mapping for at least some memory pages of the spare memory pages.

Abstract: A light emitting device, a transmitter, and a silicon photonics chip, among other things, are disclosed. An illustrative light emitting device is disclosed to include a silicon substrate, a waveguide disposed on or integrated in the silicon substrate, where the waveguide includes a wide waveguide section at a first end and a narrow waveguide section at a second end, a first metal pad disposed over the wide waveguide section and at least partially across the first end of the waveguide, and a second metal pad disposed over the wide waveguide section, distanced away from the first metal pad. Electrical current passing between the first metal pad and the second metal pad may cause light to be produced in the wide waveguide section and the light produced in the wide waveguide section is at least partially reflected by the first metal pad and directed to the narrow waveguide section for transmission.

Abstract: In one embodiment, a network device, including a network interface to receive packets over a packet data network, and a hierarchical policer to provide queue fairness for a plurality of network flows competing for access to a multiplex network receive queue, and including level one meters to label the received packets, a level two meter to receive at least some of the labeled packets and relabel the at least some labeled packets, and queueing logic add the packets labeled with a first label-type to the multiplex network receive queue and drop the packets labeled with a third label-type.

Abstract: An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.

Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device, to perform operations including receiving, from a thermal sensor group including thermal sensors, hotspot temperature measurements with respect to a hotspot. Each temperature measurement is received from a respective thermal sensor. The operations further include determining, from the temperature measurements, a generalized hotspot temperature measurement for the thermal sensor group.

Abstract: A system includes a processing device to receive a video content, a quality metric, and a target bit rate for encoding the video content. The system includes encoding hardware to perform frame encoding on the video content and a controller coupled between the processing device and the encoding hardware. The controller is programmed with machine instructions to generate first QP values on a per-frame basis using a frame machine learning model with a first plurality of weights. The first plurality of weights depends at least in part on the quality metric and the target bit rate. The controller is further programmed to provide the first QP values to the encoding hardware for rate control of the frame encoding.

Abstract: In one embodiment, a system includes a network interface controller including a device interface to connect to a processing device and receive a time synchronization marker message from an application running on the processing device, a network interface to send packets over a network, and packet processing circuitry to process the time synchronization marker message for sending via the network interface over the network to a slave clock device, generate a time synchronization follow-up message including a timestamp indicative of when the synchronization marker message egressed the network interface, and process the time synchronization follow-up message for sending via the network interface over the network to the slave clock device.

Abstract: A data compression system comprising computer memory to store plural compression algorithms and a hardware processor to apply compression algorithm/s to incoming data items, wherein the compression algorithm to be applied to individual data item/s from among the incoming data items is selected, from among the plural compression algorithms, by the hardware processor, depending at least on the individual data item.

Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.

Abstract: In one embodiment, a system includes a storage device controller including a first controller to read commands from a submission queue stored in a shared memory, provide the commands to a second controller, and write completion notices received from the second controller to a completion queue in the shared memory, and the second controller to receive the commands from the first controller, perform storage operations with a non-volatile memory responsively to receiving the commands, generate the completion notices responsively to performing the storage operations, provide the completion notices to the first controller, write recovery data about the commands and the completion notices to a persistent memory, and recover from a failure responsively to retrieving the recovery data from the persistent memory.

Abstract: Systems and methods are described herein for an electro-absorption modulator (EAM) device. An example EAM device comprises an optical waveguide comprising a waveguide core configured to facilitate propagation and modulation of an optical signal therethrough; a segmented structure comprising diode segments disposed on the waveguide; and an electrical transmission line operatively coupled to the diode segments. The electrical transmission line is configured to facilitate propagation of an electrical signal therethrough. The electrical transmission line includes a first transmission line rail and a second transmission line, where a first subset of diode segments is operatively coupled to the first transmission line rail and a ground rail, and a second subset of diode segments is operatively coupled to the second transmission line and the ground rail. The diode segments from the first subset are disposed alternately with the diode segments from the second subset.

Abstract: Apparatus and method for improved network resource management are described herein. An example computing apparatus comprises a network adapter configured to: receive, via a network connection, a data packet from the communication network; determine, from the first memory block, a value of an extended portion of a local counter associated with the network connection in response to receiving the data packet; capture, from the second memory block, a value of a global counter; compare the value of the extended portion of the local counter with the value of the global counter; and in an instance in which the comparison identifies a mismatch: update the value of the extended portion of the local counter based on the value of the global counter; and set a current value of a bit indicating a status of the network connection, wherein the bit is associated with the plurality of bits.

Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.

Abstract: Apparatus and method for improved network resource management are described herein. An example computing apparatus comprises a network adapter configured to: receive, via a network connection, a data packet from the communication network; determine, from the first memory block, a value of an extended portion of a local counter associated with the network connection in response to receiving the data packet; capture, from the second memory block, a value of a global counter; compare the value of the extended portion of the local counter with the value of the global counter; and in an instance in which the comparison identifies a mismatch: update the value of the extended portion of the local counter based on the value of the global counter; and set a current value of a bit indicating a status of the network connection, wherein the bit is associated with the plurality of bits.

Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.