Patents Assigned to Mellanox Technologies Ltd.
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Publication number: 20240142730Abstract: A network interface device which may include: an elongated frame having a first end, a second end, and, between the first and second ends, a top wall, a bottom wall opposing the top wall, a first lateral wall, and a second lateral wall opposing the first lateral wall; wherein the top wall includes: a first longitudinal portion that is adjacent to the first end of the frame; and a second longitudinal portion that is adjacent to the second end of the frame and whose outer surface slopes towards its inner surface in a direction of the second end of the frame.Type: ApplicationFiled: October 31, 2022Publication date: May 2, 2024Applicant: Mellanox Technologies, Ltd.Inventors: Yaniv KAZAV, Andrey Ger, Nimer Hazin, Igal Gutman
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Patent number: 11973694Abstract: In one embodiment, an in-network compute resource assignment system includes a network device to receive a request to select resources to perform a processing job, wherein the request includes at least one resource requirement of the processing job, and end point devices assigned to perform the processing job, a memory to store a state of in-network compute-resources indicating resource usage of the in-network compute-resources by other processing jobs, and a processor to manage the stored state, and responsively to receiving the request, selecting ones of the in-network compute-resources to perform the processing job based on: (a) a network topology of a network including the in-network compute-resources; (b) the state of the in-network compute-resources; and (c) the at least one resource requirement of the processing job.Type: GrantFiled: March 30, 2023Date of Patent: April 30, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Yishai Oltchik, Gil Bloch, Daniel Klein, Tamir Ronen
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Patent number: 11973696Abstract: A network device includes one or more ports, a packet processor, and a memory management circuit. The one or more ports are to communicate packets over a network. The packet processor is to process the packets using a plurality of queues. The memory management circuit is to maintain a shared buffer in a memory and adaptively allocate memory resources from the shared buffer to the queues, to maintain in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by a defined subset of the queues, to identify in the subset a queue that (i) requires additional memory resources, (ii) is not eligible for additional allocation from the shared buffer, and (iii) meets an eligibility condition for the shared-reserve memory pool, and to allocate memory resources to the identified queue from the shared-reserve memory pool.Type: GrantFiled: January 31, 2022Date of Patent: April 30, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Niv Aibester, Barak Gafni
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Patent number: 11968285Abstract: A network device includes one or more ports, and action-select circuitry. The ports are to exchange packets over a network. The act-ion-select circuitry is to determine, for a given packet, a first search key based on a first header field of the given packet, and a second search key based on a second header field of the given packet, to compare the first search key to a first group of compare values, to output a multi-element vector responsively to a match between the first search key and a first compare value, to generate a composite search key by concatenating the second search key and the multi-element vector, to compare the composite search key to a second group of compare values, and, responsively to a match between the composite search key and a second compare value, to output an action indicator for applying to the given packet.Type: GrantFiled: February 24, 2022Date of Patent: April 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Gil Levy, Aviv Kfir
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Patent number: 11968126Abstract: A method includes providing a library of hardware-agnostic packet-processing functions. A functional hardware-agnostic specification of a packet-processing pipeline, for use in a network device, is received from a user. The specification is defined in terms of one or more of the packet-processing functions draws from the library. A hardware-specific design of the packet-processing pipeline, which is suited to given hardware, is derived from the specification.Type: GrantFiled: September 29, 2022Date of Patent: April 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Roni Bar Yanai, Jiawei Wang, Yossef Efraim, Chen Rozenbaum
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Patent number: 11967963Abstract: An Integrated Circuit (IC) includes feedback control-loop (FCL) circuitry to generate a delay-compensated output signal responsively to an input reference signal. The FCL circuitry includes a main feedback path, a first subtractor, a delay-compensation feedback path, and a second subtractor. The main feedback path is to generate a main feedback signal responsively to the delay-compensated output signal. The first subtractor is to generate a non-compensated output signal responsively to a difference between the main feedback signal and the input reference signal. The delay-compensation feedback path is to generate a delay-compensation feedback signal responsively to the delay-compensated output signal. The second subtractor is to generate the delay-compensated output signal responsively to a difference between the non-compensated output signal and the delay-compensation feedback signal.Type: GrantFiled: March 9, 2022Date of Patent: April 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventor: Raanan Ivry
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Patent number: 11968089Abstract: A network device (ND) includes packet processing circuitry and performance optimization circuitry. The packet processing circuitry is connected to a network and is configured to process communication packets for communicating over the network. The packet processing circuitry includes a plurality of configuration registers for setting one or more operation parameters of the ND. The performance optimization circuitry is configured to improve a performance measure of the ND by iteratively calculating the performance measure and adjusting values of one or more of the configuration registers based on the performance measure.Type: GrantFiled: November 7, 2022Date of Patent: April 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ido Gilboa, Shay Aisman, Sagi Arieli, Oren Vaserberger, Amit Mandelbaum, Doron Haritan Kazakov, Natali Shechtman, Iftah Levi, Amir Ancel
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Patent number: 11966310Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.Type: GrantFiled: November 7, 2022Date of Patent: April 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Alon Singer, Ziv Battat, Liron Mula
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Patent number: 11966319Abstract: A method for data-center management includes, in a data center including multiple components, monitoring a plurality of performance measures of the components. A set of composite metrics is automatically defined, each composite metric including a respective weighted combination of two or more performance measures from among the performance measures. Baseline values are established for the composite metrics. An anomalous deviation is detected of one or more of the composite metrics from the respective baseline values.Type: GrantFiled: February 23, 2021Date of Patent: April 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Vadim Gechman, Tamar Viclizki, Gaby Vanesa Diengott, David Slama, Samir Deeb, Shie Mannor, Gal Chechik
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Patent number: 11966355Abstract: A network adapter includes a network interface that communicates packets over a network, a host interface connected locally to a host processor and to a host memory, and processing circuitry, coupled between the network interface and the host interface, and is configured to receive in a common queue, via the host interface, (i) a processing work item specifying a source buffer in the host memory, a data processing operation, and a first address in the host memory, and (ii) an RDMA write work item specifying the first address, and a second address in a remote memory. In response to the processing work item, the processing circuitry reads data from the source buffer, applies the data processing operation, and stores the processed data in the first address. In response to the RDMA write work item the processing circuitry transmits the processed data, over the network, for storage in the second address.Type: GrantFiled: December 19, 2018Date of Patent: April 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ariel Shahar, Roee Moyal, Ali Ayoub, Michael Kagan
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Patent number: 11963309Abstract: Processes for laminating a conductive-lubricant coated Printed Circuit Board (PCB) are disclosed. An example laminated PCB may include a lamination stack that may further include a core, an adhesive layer, and at least one graphene-metal structure or at least one hexagonal Boron Nitride metal (h-BN-metal) structure. The materials of the PCB may change in accordance with the invention described herein, including the materials of the core, the materials of the conductive-lubricant coatings, or the metal layers of the conductive-lubricant-metal structures. Doping processes for each change in materials used are also described herein. The conductive-lubricant of the conductive-lubricant-metal structure will promote high frequency performance and heat management within the PCB. Furthermore, a removal process of those materials post-lamination is described herein to promote protection of materials and subsequent removal of protective layers without breakage or tearing.Type: GrantFiled: July 1, 2021Date of Patent: April 16, 2024Assignees: MELLANOX TECHNOLOGIES, LTD., BAR-ILAN UNIVERSITY, PCB TECHNOLOGIES LTD.Inventors: Boaz Atias, Elad Mentovich, Yaniv Rotem, Doron Naveh, Adi Levi, Yosi Ben-Naim, Yaad Eliya, Shlomo Danino, Eran Lipp, Alon Rubinstein, Ran Hasson Ruso
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Patent number: 11962481Abstract: Methods, systems, and computer program products to combine multiple telemetry data signals to generate a single higher resolution signal. In embodiments, the method includes: modulating a sampling of telemetry data by at least two network devices; receiving telemetry data from the at least two network devices; combining the received telemetry data; and determining a status of the network and/or network devices based on a processing of the combined telemetry data.Type: GrantFiled: May 26, 2022Date of Patent: April 16, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ran Sandhaus, Vladimir Shalikashvili, Zachi Binshtock
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Patent number: 11955778Abstract: A method and system for large scale Vertical-Cavity Surface-Emitting Laser (VCSEL) binning from wafers to be compatible with a Clock-Data Recovery Unit (CDRU) and/or a VCSEL driver are provided. An illustrative method of binning is provided that includes: for at least a portion of VCSELs on a wafer, measuring a set of representative parameters of the VCSELs, of predetermined DC or small-signal values, and sorting the measured VCSELs into clusters according to the measured set of representative parameters of the VCSELs; further sorting the clusters into sub-groups that comply with specifications of the VCSEL driver; and providing a feedback signal to the CDRU for equalizing control signals provided to the VCSEL driver.Type: GrantFiled: January 25, 2021Date of Patent: April 9, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Tali Septon, Itshak Kalifa, Elad Mentovich, Matan Galanty, Yaakov Gridish, Hanan Shumacher, Vadim Balakhovski, Juan Jose Vegas Olmos
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Patent number: 11956160Abstract: An apparatus includes an input interface to receive incoming packets from a first network device and an output interface to send outgoing packets to a second network device. Media access control security (MACsec) circuitry is coupled between the input interface and the output interface. Bypass flow-control (FC) circuitry is coupled between the input interface and the MACsec circuitry. The bypass FC circuitry is to detect an FC packet in the incoming packets and pass the FC packet passively to the output interface to enable end-to-end flow control directly between the first network device and the second network device.Type: GrantFiled: June 1, 2021Date of Patent: April 9, 2024Assignee: Mellanox Technologies, Ltd.Inventors: Zachy Haramaty, Liron Mula, Alon Singer, Eduard Kvetny, Aviv Kfir
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Publication number: 20240113943Abstract: Systems, computer program products, and methods are described herein for dynamic reconfiguration of network communications. An example system includes a first network pod including a first set of network ports, a second network pod including a second set of network ports, a set of network cores, and a first intermediate network switch. The first intermediate switch operatively couples the first network pod, the second network pod, and the set of network cores. The first intermediate network switch is configured to selectively establish full bisectional bandwidth data communication between a subset of the set of network cores, a subset of the first set of network ports, and a subset of the second set of network ports.Type: ApplicationFiled: October 12, 2022Publication date: April 4, 2024Applicant: Mellanox Technologies, Ltd.Inventors: Ioannis (Giannis) PATRONAS, Paraskevas BAKOPOULOS, Dimitrios SYRIVELIS, Elad MENTOVICH, Eitan ZAHAVI, Louis Bennie CAPPS, Jr., Prethvi Ramesh KASHINKUNTI, Julie Irene Marcelle BERNAUER, Nikolaos TERZENIDIS
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Patent number: 11949463Abstract: Various embodiments of the present disclosure are directed to accessing a quantum communication channel undetected and/or characterizing this communication channel based upon attempted access. An example method includes accessing a quantum communication channel transmitting one or more qubits. The method includes the introduction of a noise signal to the quantum communication channel and then applying in its absence one or more weak or variable-strength measurements to the quantum communication channel. A strength of at least one measurement of the one or more measurements is based at least in part upon the current noise signal. The method further includes obtaining information associated with the one or more qubits based on the one or more measurements.Type: GrantFiled: July 12, 2023Date of Patent: April 2, 2024Assignee: Mellanox Technologies, Ltd.Inventors: Tali Septon, Elad Mentovich, Moshe B Oron, Yonatan Piasetzky, Yuval Idan, Eliahu Cohen, Avshalom C Elitzur, Taylor Lee Patti
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Publication number: 20240106756Abstract: A computing device which may include a programmable hardware device and a microcontroller to, based on a policy and parameters of a packet received by the programmable hardware device, program a rule in the programmable hardware device, the rule indicating how to process the packet.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: Mellanox Technologies, Ltd.Inventors: Roni BAR YANAI, Itai GEFFEN, Ori KAM
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Patent number: 11941722Abstract: A kernel comprising at least one dynamically configurable parameter is submitted by a processor. The kernel is to be executed at a later time. Data is received after the kernel has been submitted. The at least one dynamically configurable parameter of the kernel is updated based on the data. The kernel having the at least one updated dynamically configurable parameter is executed after the at least one dynamically configurable parameter has been updated.Type: GrantFiled: October 13, 2021Date of Patent: March 26, 2024Assignee: Mellanox Technologies, Ltd.Inventors: Sayantan Sur, Stephen Anthony Bernard Jones, Shahaf Shuler
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Patent number: 11940935Abstract: A computerized system operating in conjunction with computerized apparatus and with a fabric target service in data communication with the computerized apparatus, the system comprising functionality residing on the computerized apparatus, and functionality residing on the fabric target service, which, when operating in combination, enable the computerized apparatus to coordinate access to data.Type: GrantFiled: April 19, 2021Date of Patent: March 26, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Eliav Bar-Ilan, Oren Duer, Maxim Gurtovoy, Liran Liss, Aviad Shaul Yehezkel
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Patent number: 11940660Abstract: An OSFP optical transceiver having split multiple fiber optical port using reduced amount of MPO terminations is provided that includes two adjacent sockets integrated into the optical port of the OSFP optical transceiver. The two adjacent sockets are vertically oriented with respect to the mounting baseplate of the OSFP optical transceiver, and each of the two adjacent sockets is adapted to receive an MPO receptacle that terminates the proximal end of a bundle of fibers. The OSFP optical transceiver also includes an optical connection between each socket and a corresponding lens in the OSFP optical transceiver, for transmitting optical signals received from other transceivers into the OSFP optical transceiver and optical signals generated in the OSFP optical transceiver to other transceivers.Type: GrantFiled: February 6, 2023Date of Patent: March 26, 2024Assignee: Mellanox Technologies, Ltd.Inventors: Andrey Ger, Rony Setter, Yaniv Kazav