Abstract: Various embodiments of the present disclosure provide for generating and managing a digital ledger access system and its associated objects. An example method is configured for securing objects in a digital ledger of objects by identifying an object from amongst a plurality of objects in the digital ledger of objects and generating a quantum token for attachment with the object. The method includes deriving one or more classical public keys associated with the quantum token and determining an attempt to access the object. The method provides access to the object in response to a validation of the classical public key based on the quantum token, and the method precludes access to the object in response to an invalidation of the classical public key based on the quantum token.

Abstract: A networking device and system are described, among other things. An illustrative system is disclosed to include a congestion controller that manages traffic across a network fabric using receiver-based packet scheduling and a networking device that employs the congestion controller for data flows qualified as a large data flow but bypasses the congestion controller for data flows qualified as a small data flow. For example, the networking device may receive information describing a data flow directed toward a processing network; determine, based on the information describing the data flow, a size of the data flow; determine the size of the data flow is below a predetermined flow threshold; and in response to determining that the size of the data flow is below a predetermined threshold, bypass the congestion controller.

Abstract: A network adapter includes a host interface and a scheduler. The host interface is configured to receive, from one or more hosts, packets for transmission to respective destinations over a network. The scheduler is configured to synchronize to a time-division schedule that is employed in the network, the time-division schedule specifying (i) multiple time-slots and (ii) multiple respective groups of the destinations that are reachable during the time-slots, and, based on the time-division schedule, to schedule transmission times of the packets to the network on time-slots during which the respective destinations of the packets are reachable.

Abstract: A network device includes one or more ports, and action-select circuitry. The ports are to exchange packets over a network. The action-select circuitry is to determine, for a given packet, a first search key based on a first header field of the given packet, and a second search key based on a second header field of the given packet, to compare the first search key to a first group of compare values, to output a multi-element vector responsively to a match between the first search key and a first compare value, to generate a composite search key by concatenating the second search key and the multi-element vector, to compare the composite search key to a second group of compare values, and, responsively to a match between the composite search key and a second compare value, to output an action indicator for applying to the given packet.

Abstract: A digital-to-charge converter, a digital-to-analog converter, and a method of operating a digital-to-charge converter are provided. An illustrative method of operating a digital-to-charge converter is provided that includes: receiving a digital input signal at the digital to charge converter, charging one or more capacitors during a pre-evaluation period, where the one or more capacitors are charged with a supply voltage based the digital input signal, disconnecting the one or more capacitors from the supply voltage during an evaluation period, and generating an analog output signal from the digital to charge converter based on an evaluation of charge of the one or more capacitors during the evaluation period.

Abstract: In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.

Abstract: A network device includes a plurality of ports, processing circuitry, and control circuitry. The ports are to receive communication traffic from a plurality of processing devices. The processing circuitry is to process the communication traffic received via the ports. The control circuitry is to assess one or more electrical-current consumption values associated with at least the network device, and, depending on the electrical-current consumption values, to control a traffic slew-rate of the communication traffic of at least a port among the ports to remain within a specified slew-rate range, the traffic slew-rate being defined as a rate at which a bandwidth of the communication traffic received via the port changes as a function of time.

Abstract: A method and system are provided for limiting unnecessary data traffic on the data busses connecting the various levels of system memory. Some embodiments may include processing an invalidation command associated with a system or network operation requiring temporary storage of data in a local memory area. The invalidation command may comprise a memory location indicator capable of identifying the physical addresses of the associated data in the local memory area. Some embodiments may preclude the data associated with the system or network operation from being written to a main memory by invalidating the memory locations holding the temporary data once the system or network operation has finished utilizing the local memory area.

Abstract: Embodiments are disclosed for a quantum key distribution (QKD) enabled intra-datacenter network. An example system includes a first QKD device and a second QKD device. The first QKD device includes a first quantum-enabled port and a first network port. The second QKD device includes a second quantum-enabled port and a second network port. The first quantum-enabled port of the first QKD device is communicatively coupled to the second quantum-enabled port of the second QKD device via a QKD link associated with quantum communication. Furthermore, the first network port of the first QKD device is communicatively coupled to a first network switch via a first classical link associated with classical network communication. The second network port of the second QKD device is communicatively coupled to a second network switch via a second classical link associated with classical network communication.

Abstract: Processes for localized lasering of a lamination stack and graphene-coated printed circuit board (PCB) are disclosed. An example PCB may include a lamination stack, post-lamination, that may further include a core, an adhesive layer, and at least one graphene-metal structure. A top layer of graphene of the graphene-metal structure may have never been grown before the lamination process or may have been removed post-lamination such that a portion of the top layer of graphene is missing. The localized lasering process described herein may grow (for the first time) or re-grow the graphene layer of the exposed portion of the metal layer without adverse effects to the rest of the lamination stack or PCB and while promoting a uniform layer of graphene on the top surface. A process of growing graphene through application of molecular layer and a self-assembled monolayer (SAM), are also described herein.

Abstract: In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

Abstract: In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.

Abstract: Traveling wave cascaded micro ring modulators (TW-CMRMs) are provided. An example TW-CMRM includes an optical bus, an electrical transmission line, and at least two micro ring modulators (MRMs) operatively coupled to the optical bus and the electrical transmission line. The electrical transmission line includes a cathode transmission line and an anode transmission line. The at least two MRMs are cascaded in a series connection, and the at least two cascaded MRMs include a first terminal and a second terminal respectively. The at least two cascaded MRMs collectively modulate a phase and/or an amplitude of an optical input signal received from an optical signal source.

Abstract: A system which facilitates efficient operation of plural agents, the system comprising a device which services the plural agents; and functionality which resides on the device and which provides a given quality of service, defined in terms of at least one resource, to at least one subset of agents from among the plural agents.

Abstract: A controller includes one or more ports and a processor. The one or more ports are to communicate with a network that includes multiple network devices. The processor is to receive, from a network device in the network, a request to perform a software update in the network device, to evaluate a permission condition in response to the request, to send to the network device a response granting the request when the permission condition is met, and to at least temporarily deny the request when the permission condition is not met.

Abstract: A network adapter includes a host interface, a network interface, a packet processor, and a telemetry handler. The host interface is to communicate with a host. The network interface is to send packets to a network. The packet processor is to process the packets prior to sending the packets to the network. The telemetry handler is to receive from the host, over the host interface, an indication specifying a flow or application, to mark one or more packets associated with the flow or application with a specified identifier in response to the indication, and to send the marked packets using the packet processor to the network via the network interface.

Abstract: A network interface controller includes processing circuitry configured to pair with a local root of trust of a host device connected to the network interface controller and provide a key to an encryption device of the host device that enables the encryption device to encrypt data of one or more host device applications using the key. The encrypted data are stored in host device memory. The processing circuitry is configured to share the key with a remote endpoint and forward the encrypted data from the host device memory to the remote endpoint.

Abstract: A device may include: a frame having an interior; an electronic component; a heat conducting body in thermal contact with the electronic component; a conduit containing a liquid coolant, the conduit being coupled to the heat conducting body to deliver the liquid coolant to and from the heat conducting body; and a pump positioned within the interior of the frame, the pump being removably insertable into the interior of the frame and being removably couplable to the conduit to circulate the liquid coolant through the conduit.

Abstract: In one embodiment, data communication device includes a network interface to receive first packets over a network from another network device via a switch, which includes a buffer associated with a variable buffer delay, and packet processing circuitry to compute respective measures of delay over the network to the other network device over time responsively to the received first packets, find a minimum measure of delay over the network to the other network device responsively to at least some of the computed respective measures of delay, estimate a current measure of buffer delay of the buffer responsively to the found minimum measure of delay and a current one of the computed respective measures of delay, set a packet processing parameter responsively to the estimated current measure of buffer delay, and process second packets responsively to the set packet processing parameter.

Abstract: A network device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the network device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The instruction processor includes architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and the match-action circuitry is to write into the architectural registers information for performing the programmable action.