Patents Assigned to Mellanox Technologies Ltd.
  • Patent number: 10473857
    Abstract: A waveguide having a gradient-index (GRIN) waveguide lateral coupler is provided. In an example embodiment, the waveguide comprises an active region. The refractive index profile of the active region is non-constant.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: November 12, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yaakov Gridish, Eran Aharon, Elad Mentovich, Sylvie Rockman
  • Patent number: 10476803
    Abstract: A network element connected to a data network holds a flow of data packets in a queue and periodically determines a metric of the queue. Responsively to a predetermined value of the metric the queue is associated with an elephant flow or a mouse flow. The packets are marked according to the associated flow, and the network element sends the marked packets into the data network. Other network elements process the packets according to the associated flow marked therein.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 12, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Alex Shpiner, Liran Liss, Matty Kadosh
  • Patent number: 10474778
    Abstract: Methods and systems for designing an integrated circuit device are described. The method includes receiving RTL descriptions of the whole device and generating lower level component descriptions. The method further includes grouping the component descriptions into blocks, analyzing the component descriptions, and identifying block internal removable components based on the analysis. The method further includes removing the removable components. Reduced design is converted into gate-level descriptions. Finally, the method includes executing high quality and high efficiency device TOP level physical implementation and generation of physical and timing constrains for block level design.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: November 12, 2019
    Assignee: Mellanox Technologies Ltd.
    Inventor: Alexander Martfeld
  • Patent number: 10467161
    Abstract: Apparatus for communications includes a CPU, a system memory, and a network interface controller (NIC), which is configured to receive incoming data packets from a network, to post the received data packets in a designated queue for delivery to the CPU. The NIC issues interrupts to the CPU in response to the incoming data packets at a rate determined, for the designated queue, in accordance with an interrupt moderation parameter that is set for the queue. During each of a succession of monitoring periods, the CPU measures for the designated queue a current throughput of the incoming data packets and a current rate of interrupts, makes a comparison between the current measured throughput and rate of interrupts to the throughput and rate of interrupts that were measured during a preceding period in the succession, and selects and applies an update to the interrupt moderation parameter responsively to the comparison.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 5, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Tal Gilboa, Gil Rockah, Achiad Shochat, Amir Ancel
  • Patent number: 10466422
    Abstract: An optical device includes a first waveguide having a longitudinal axis and a first end facet inclined at a non-normal angle to the longitudinal axis, and a second waveguide, which has a second end facet and is fixed with the second end facet in proximity to and parallel with the first end facet. An actuator is coupled to move the first end facet of the first waveguide in a direction transverse to the longitudinal axis between a first position in which a distance between the first and second end facets is less than 25 nm, and a second position in which the distance between the first and second end facets is greater than 300 nm.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: November 5, 2019
    Assignees: Mellanox Technologies, Ltd., Yissum Research Development Company of the Hebrew University LTD.
    Inventors: Eran Aharon, Dan Mark Marom, Elad Mentovich
  • Patent number: 10462075
    Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 29, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Freddy Gabbay, Ido Bukshpan, Alon Webman, Miriam Menes, George Elias, Noam Katz Abramovich
  • Patent number: 10460060
    Abstract: A method for circuit design automation includes receiving an initial RTL definition of a design of a circuit, and synthesizing an initial netlist of the circuit based on the initial RTL definition. After synthesizing the initial netlist, an updated RTL definition containing a design change and a corresponding updated netlist are received. The updated RTL definition and netlist are automatically analyzed to identify first and second logical relations that were changed in the RTL definition and netlist, respectively. A notification is issued of sets of the endpoints between which the first logical relations were changed without changes to the second logical relations or vice versa. For the sets of the endpoints between which both the first logical relations and the second logical relations were changed, the equivalence between the first and second logical relations is automatically verified.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 29, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Or Davidi, Roy Armoni
  • Patent number: 10461507
    Abstract: A vertical-cavity surface-emitting laser (VCSEL), substrate emitting VCSEL, and multi-beam emitting device and corresponding manufacturing processes are provided. An example VCSEL comprises a substrate having a first surface and a second surface; an output coupling mirror disposed on the second surface of the substrate; a high reflectivity mirror; and an active cavity material structure disposed between the output coupling mirror and the high reflectivity mirror. The active cavity material structure comprises a first current-spreading layer, a second current-spreading layer, an active region disposed between the first current-spreading layer and the second current-spreading layer, and a tunnel junction overgrown by the second current spreading layer, wherein the tunnel junction is disposed adjacent the active region. The VCSEL is configured to emit radiation outward through the first surface of the substrate.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: October 29, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Alexei Sirbu, Vladimir Iakovlev, Yuri Berk, Elad Mentovich
  • Patent number: 10462060
    Abstract: Packet flows received in a data network are assigned to respective entries of a database. During an accumulation interval byte counts of the assigned packet flows are accumulated in the respective database entries. The packet flows are classified as elephant flows when differences between the byte counts and a reference byte count exceed a threshold and are reported after expiration of the accumulation interval.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 29, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Jacob Ruthstein, David Mozes, Dror Bohrer, Ariel Shahar, Lior Narkis, Noam Bloch
  • Patent number: 10454991
    Abstract: A network interface device includes a host interface for connection to a host processor and a network interface, which is configured to transmit and receive data packets over a network, and which comprises multiple distinct physical ports configured for connection to the network. Processing circuitry is configured to receive, via one of the physical ports, a data packet from the network and to decide, responsively to a destination identifier in the packet, whether to deliver a payload of the data packet to the host processor via the host interface or to forward the data packet to the network via another one of the physical ports.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: October 22, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Noam Bloch, Ariel Shachar, Michael Kagan, Lior Narkis, Shlomo Raikin
  • Patent number: 10445279
    Abstract: A computer system includes a system bus having multiple lanes, one or more peripheral devices, and a bus controller. The peripheral devices are coupled to the system bus. The bus controller is configured to receive, from one or more of the peripheral devices, respective indications of numbers of the lanes requested by the peripheral devices, and to configure the system bus in response to the indications.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 15, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yuval Itkin, Assad Khamaisee
  • Patent number: 10444453
    Abstract: An adapter includes an electrical male connector, an electrical female connector, an electronic circuit and one or more visual indicators. The electrical male connector is configured for plugging into a receptacle of a first electro-optical transceiver type having N signal lanes. The electrical female connector is configured to receive a male connector of a second electro-optical transceiver type having M signal lanes, M smaller than N. The electronic circuit is configured to route a partial subset of M signal lanes from among the N signal lanes, between the electrical male connector and the electrical female connector. One or more visual indicators are configured to display a status of one or more network ports mapped to one or more of the signal lanes in the partial subset.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: October 15, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Assad Khamaisee, Avraham Ganor
  • Patent number: 10436841
    Abstract: A method for circuit design includes providing one or more wrapper cells for use with a library of standard cells in design of an IC. Each wrapper cell has geometrical dimensions matching a corresponding group of one or more of the standard cells and defines an electrical path, including at least one via, from a location of a terminal in a lower metal layer in the standard cells in the corresponding group to a location in an upper metal layer. A computerized place-and-route tool receives a layout of the IC including a wrapper cell superimposed over one of the standard cells in the corresponding group. The place-and-route tool automatically routes a signal connection through the upper metal layer and the at least one via defined by the superimposed wrapper cell to the predefined signal terminal in the lower metal layer in the one of the standard cells.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 8, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Ido Bourstein, Ofer Shalev
  • Patent number: 10430374
    Abstract: A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 1, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Adi Menachem, Ariel Shahar, Noam Bloch, Diego Crupnicoff, Michael Kagan
  • Patent number: 10396527
    Abstract: A vertical-cavity surface-emitting laser (VSCEL) and method for producing a VCSEL are described, the VCSEL including an undercut active region. The active region of the VCSEL is undercut relative to current-spreading layers of the VCSEL, such that a width of a tunnel junction of the VCSEL overgrown by a current spreading layer is less than a width of an active region of the VCSEL, and a width of the active region of the VCSEL is less than a width of the overgrown current-spreading layer, such that the VCSEL including the undercut active region is configured to transmit data at speeds greater than 25 gigabits/second.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: August 27, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Alexei Sirbu, Vladimir Iakovlev, Yuri Berk, Itshak Kalifa, Elad Mentovich, Sylvie Rockman
  • Patent number: 10394060
    Abstract: An method for characterizing a modulator for fabricating a silicon photonics circuit and an apparatus (e.g., a silicon photonics wafer) made via the method are described. The method includes determining an absorption spectrum of a modulator and determining, based at least on the determined absorption spectrum, an operational bandwidth of the modulator. The method further includes selecting a laser for coupling with the modulator using the operational bandwidth of the modulator. In this way, the laser is selected such that it has an emission bandwidth that corresponds to the operational bandwidth of the modulator.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: August 27, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Elad Mentovich, Sylvie Rockman, Jacob Levy, Shai Cohen
  • Patent number: 10394653
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also discussed are techniques to add new capabilities to protocols, such as the CHI protocol to achieve “Total Store Order” (TSO) among multiple devices, such as PCI Express devices, in a cost effective manner.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: August 27, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventor: Mark Rosenbluth
  • Patent number: 10394747
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 27, 2019
    Assignee: Mellanox Technologies Ltd.
    Inventors: Peter Paneah, Carl G. Ramey, Gil Moran, Adi Menachem, Christopher J. Jackson, Ilan Pardo, Ariel Shahar, Tzuriel Katoa
  • Patent number: 10387332
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: August 20, 2019
    Assignee: Mellanox Technologies Ltd.
    Inventors: Christopher D. Metcalf, Bruce Edwards, Anant Agarwal, Chyi-Chang Miao, Patrick Robert Griffin
  • Patent number: 10387358
    Abstract: A plurality of Peripheral Component Interconnect Express (PCIe) endpoints of a multi-socket network interface device are attached to a host for exchanging ingress traffic and egress traffic. An operating system of the host includes a bonding/teaming module having a plurality of network interfaces. The bonding/teaming module is configured to select one of the endpoints for the egress traffic. The network interface device has a hardware bond module configured to steer the ingress traffic to designated ones of the endpoints.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: August 20, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventor: Tzahi Oved