Abstract: A network adapter includes a host interface, a network interface, a packet processor, and a telemetry handler. The host interface is to communicate with a host. The network interface is to send packets to a network. The packet processor is to process the packets prior to sending the packets to the network. The telemetry handler is to receive from the host, over the host interface, an indication specifying a flow or application, to mark one or more packets associated with the flow or application with a specified identifier in response to the indication, and to send the marked packets using the packet processor to the network via the network interface.

Abstract: A switch, communication system, and method are provided. In one example, a communication system is described that includes a plurality of communication nodes and a switch that interconnects and facilitates a transmission of packets between the plurality of communication nodes. The communication system may be configured such that the packets are transmitted between the plurality of communication nodes by draining a demand matrix.

Abstract: A peripheral device includes a bus interface and an Address Translation Service (ATS) controller. The bus interface is to communicate over a peripheral bus. The ATS controller is to communicate over the peripheral bus, including sending address translation requests and receiving address translations in response to the address translation requests, to cache at least some of the address translations in one or more Address Translation Caches (ATCs), to estimate one or more statistical properties of the received address translations, and to configure the one or more ATCs based on the one or more statistical properties.

Abstract: Various embodiments of improved PIN-type photodiodes are provided. In an example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a second absorbing layer disposed between the first absorbing layer and the n-type contact. The first absorbing layer is characterized by a first absorption coefficient and the second absorbing layer is characterized by a second absorption coefficient. The second absorption coefficient is greater than the first absorption coefficient. In another example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a non-absorbing accelerating layer disposed between absorbing layers and non-absorbing drift layer and the n-type contact.

Abstract: Systems, computer program products, and methods are described herein for network discovery, port identification, and/or identifying fiber link failures in an optical network, in accordance with an embodiment of the invention. The present invention may be configured to sequentially connect each port of an optical switch to a network port of a server and generate, based on information associated with network devices connected to the ports, a network map. The network map may identify which network devices are connected to which ports of the optical switch and may permit dynamic port mapping for network installation, upgrades, repairs, and/or the like. The present invention may also be configured to determine a fiber link in which a failure occurred and reconfigure the optical switch to allow communication between an optical time-domain reflectometer and the fiber link to test the fiber link.

Abstract: A device receives a packet from a local network. The packet may be directed toward a cloud computing resource. The device determines that the packet is associated with a new packet flow. In response to determining that the packet is associated with the new packet flow, the device provides one or more packets from the new packet flow to a machine learning model for packet inspection. The device receives an output from the machine learning model and routes the new packet flow based on the output received from the machine learning model. The output indicates whether or not the new packet flow is associated with a network attack.

Abstract: An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress domains and one or more egress domains. The crossbar circuit includes sub-crossbar domains. An ingress control circuit associated with the one or more ingress domains may distribute packet data of the one or more packets to the sub-crossbar domains. An egress control circuit of the apparatus receives data bits associated with the packet data from egresses associated with the plurality of sub-crossbar domains. The egress control circuit may reorder or refrain from reordering the data bits based on an attribute associated with the distribution of the packet data.

Abstract: A system and method for establishing connections in a computer network supporting a remote direct memory access (RDMA) protocol, may include: generating a plurality of dummy queue pairs, each generated with dummy parameter values; and upon receiving a request to establish a connection from a first computer node in the computer network, turning one of the dummy queue pairs into a functional queue pair by changing a subgroup of the dummy parameter values to true parameter values.

Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.

Abstract: Devices, apparatuses, systems, and methods are provided for improved thermal management in networking computing devices. An example thermal management apparatus includes a housing defining a first end and a second end opposite the first end. The apparatus further includes an electronic component supported within the housing, such as a GPU. The apparatus includes a primary inlet that receives a primary airflow having a first temperature and a secondary inlet that receives a secondary airflow having a second temperature where the second temperature is different than the first temperature. The primary airflow and the secondary airflow are collectively configured to dissipate heat generated by the electronic component.

Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

Abstract: A confidential computing (CC) apparatus includes a CPU and a peripheral device. The CPU is to run a hypervisor that hosts one or more Trusted Virtual Machines (TVMs). The peripheral device is coupled to the CPU and to an external memory. The CPU includes a TVM-Monitor (TVMM), to perform management operations on the one or more TVMs, to track memory space that is allocated by the hypervisor to the peripheral device in the external memory, to monitor memory-access requests issued by the hypervisor to the memory space allocated to the peripheral device in the external memory, and to permit or deny the memory-access requests, according to a criterion.

Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is to communicate with an NVM. The processor is to store in the NVM at least a Type-Length-Value (TLV) record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least a validity indicator of the TLV record, to read the TLV record from the NVM, and to invalidate the TLV record by modifying the validity indicator stored in the non-encrypted fields, without decryption of any of the encrypted fields.

Abstract: Apparatuses, systems, and techniques for classifying a candidate uniform resource locator (URL) as malicious using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service to protect one or more computer programs executed by the host device. The security service extracts a set of features from data stored in the physical memory, the data being words in a candidate URL and numeric features of a URL structure of the candidate URL. The security service classifies, using the ML detection system, the candidate URL as malicious or benign using the set of features. The security service outputs an indication of a malicious URL responsive to the candidate URL being classified as malicious.

Abstract: An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.

Abstract: A system includes a processing device to receive a video content, a quality metric, and a target bit rate for encoding the video content. The system includes encoding hardware to perform frame encoding on the video content and a controller coupled between the processing device and the encoding hardware. The controller is programmed with machine instructions to generate first QP values on a per-frame basis using a frame machine learning model with a first plurality of weights. The first plurality of weights depends at least in part on the quality metric and the target bit rate. The controller is further programmed to provide the first QP values to the encoding hardware for rate control of the frame encoding.

Abstract: A light emitting device, a transmitter, and a silicon photonics chip, among other things, are disclosed. An illustrative light emitting device is disclosed to include a silicon substrate, a waveguide disposed on or integrated in the silicon substrate, where the waveguide includes a wide waveguide section at a first end and a narrow waveguide section at a second end, a first metal pad disposed over the wide waveguide section and at least partially across the first end of the waveguide, and a second metal pad disposed over the wide waveguide section, distanced away from the first metal pad. Electrical current passing between the first metal pad and the second metal pad may cause light to be produced in the wide waveguide section and the light produced in the wide waveguide section is at least partially reflected by the first metal pad and directed to the narrow waveguide section for transmission.

Abstract: In one embodiment, a processing device includes a memory to store a plurality of memory pages having corresponding physical memory addresses in the memory, store an active multilevel page table (MPT) mapping virtual to physical memory addresses for corresponding allocated memory pages stored in the memory, and store a floating MPT at least partially mapping virtual to physical memory addresses for corresponding spare memory pages stored in the memory, the floating and active MPT using a common mapping scheme, and a processor to receive a request to add a virtual to physical address mapping for more memory pages of the plurality of memory pages to the active MPT, and in response to receiving the request, adjoin at least part of the floating MPT to the active MPT so that the active MPT provides the virtual to physical address mapping for at least some memory pages of the spare memory pages.

Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device, to perform operations including receiving, from a thermal sensor group including thermal sensors, hotspot temperature measurements with respect to a hotspot. Each temperature measurement is received from a respective thermal sensor. The operations further include determining, from the temperature measurements, a generalized hotspot temperature measurement for the thermal sensor group.

Abstract: A data compression system comprising computer memory to store plural compression algorithms and a hardware processor to apply compression algorithm/s to incoming data items, wherein the compression algorithm to be applied to individual data item/s from among the incoming data items is selected, from among the plural compression algorithms, by the hardware processor, depending at least on the individual data item.