Abstract: A computerized system operating in conjunction with computerized apparatus and with a fabric target service in data communication with the computerized apparatus, the system comprising functionality residing on the computerized apparatus, and functionality residing on the fabric target service, which, when operating in combination, enable the computerized apparatus to coordinate access to data.

Abstract: An OSFP optical transceiver having split multiple fiber optical port using reduced amount of MPO terminations is provided that includes two adjacent sockets integrated into the optical port of the OSFP optical transceiver. The two adjacent sockets are vertically oriented with respect to the mounting baseplate of the OSFP optical transceiver, and each of the two adjacent sockets is adapted to receive an MPO receptacle that terminates the proximal end of a bundle of fibers. The OSFP optical transceiver also includes an optical connection between each socket and a corresponding lens in the OSFP optical transceiver, for transmitting optical signals received from other transceivers into the OSFP optical transceiver and optical signals generated in the OSFP optical transceiver to other transceivers.

Abstract: Systems, computer program products, and methods are described herein for machine learning (ML) based system for network resilience and steering. An example system monitors data movement across one or more network ports; extracts network performance indicators associated with the data movement; determines, via a machine learning (ML) subsystem, that a status of a first network port is indicative of operational failure based on at least the network performance indicators; determines that the first network port is associated with a first network port cluster; determines a redundant network port and an intermediate network switch associated with the first network port cluster; and triggers the intermediate network switch to reroute a portion of network traffic from the first network port to the redundant network port in response to the status of the first network port.

Abstract: Systems, computer program products, and methods are described herein for machine learning (ML) based network resilience and steering. An example system monitors data traffic across one or more network ports and determines a first data traffic pattern from the data traffic. The system further determines, via a ML subsystem, that the first data traffic pattern is indicative of a security threat to a first network port. In response to determining that the first data traffic pattern is indicative of the security threat to the first network port, the system further isolates the first network port from the one or more network ports.

Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is to communicate with one or more hosts over a peripheral bus. The processing circuitry is to expose on the peripheral bus a peripheral-bus device that communicates with the one or more hosts using one or more instances of at least one bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the one or more hosts, and to complete the I/O transactions for the one or more hosts in accordance with one or more instances of at least one network storage protocol, by running at least part of a host-side protocol stack of the at least one network storage protocol.

Abstract: A device including a cable transceiver including cable electrical connections including data electrical connections and control electrical connections, and a hardware memory device, the hardware memory device storing a string identifying a cable and being electrically accessible from externally to the cable transceiver via the control electrical connections. The cable, in electrical connection with the cable electrical connections, may be included in the device. A device for verifying cable authenticity is also described, the device including interface hardware for interfacing a plurality of cables with the device, and verifier circuitry configured to verify that each of the plurality of cables is genuine based on a string stored in a hardware memory device included in each of the plurality of cables. Related apparatus and methods are also described.

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.

Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.

Abstract: An electronic device may include a receptacle cage comprising a longitudinal aperture extending along a portion of a top surface of the receptacle cage, a cooling body disposed directly on the top surface of the receptacle cage, wherein a longitudinal portion of a bottom surface of the cooling body is disposed within the longitudinal aperture on the top surface of the receptacle cage, a first conduit to deliver a liquid coolant into an interior of the cooling body, and a second conduit to deliver the liquid coolant from the interior of the cooling body.

Abstract: A classification apparatus includes a memory and a processor. The memory is configured to store rules corresponding to a corpus of rules in respective rule entries, each rule includes a respective set of unmasked bits having corresponding bit values, and at least some of the rules include masked bits. The rules in the corpus conform to respective Rule Patterns (RPs), each RP defining a respective sequence of masked and unmasked bits. The processor is configured to cluster the RPs, using a clustering criterion, into extended Rule Patterns (eRPs) associated with respective hash tables including buckets for storing rule entries. The clustering criterion aims to minimize an overall number of the eRPs while meeting a collision condition that depends on a specified maximal number of rule entries per bucket.

Abstract: A communication apparatus includes input circuitry, an encapsulator, transmission circuitry and flow control circuitry. The input circuitry is to receive packets from a data source in accordance with a first communication protocol that employs credit-based flow control. The encapsulator is to buffer the packets in a memory buffer and to encapsulate the buffered packets in accordance with a second communication protocol. The transmission circuitry is to transmit the encapsulated packets over a communication link in accordance with the second communication protocol. The flow control circuitry is to receive from the encapsulator buffer status indications that are indicative of a fill level of the memory buffer, and to exchange credit messages with the data source, in accordance with the credit-based flow control of the first communication protocol, responsively to the buffer status indications.

Abstract: An electronic circuit may include at least two capacitors arranged in parallel; at least two resistors arranged in series; a positive supply voltage connected to the resistors; a negative supply voltage connected to the resistors, the resistors producing a reference signal; a source circuit producing a source signal and connected to the positive supply voltage and negative supply voltage; and a receiving circuit connected to the positive supply voltage and negative supply voltage, and receiving the source signal and reference signal.

Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.

Abstract: A method for collective communications includes invoking a collective operation over a group of computing processes in which the processes concurrently transmit and receive data to and from other processes in the group via a communication medium. Messages are composed for transmission by source processes including metadata indicating how the data to be transmitted by the source processes in the collective operation are to be handled by destination processes that are to receive the data and also including in at least some of the messages the data to be transmitted by one or more of the source processes to one or more of the destination processes. The composed messages are transmitted concurrently from the source processes to the destination processes in the group over the communication medium. The data are processed by the destination processes in response to the metadata included in the messages received by the destination processes.

Abstract: A device may include a frame, a first leg extending from the frame, and a second leg extending from the frame, wherein each of the first leg and the second leg is curved in a respective direction, the respective directions being different.

Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.

Abstract: A method and system are provided for limiting unnecessary data traffic on the data busses connecting the various levels of system memory. Some embodiments may include processing an invalidation command associated with a system or network operation requiring temporary storage of data in a local memory area. The invalidation command may comprise a memory location indicator capable of identifying the physical addresses of the associated data in the local memory area. Some embodiments may preclude the data associated with the system or network operation from being written to a main memory by invalidating the memory locations holding the temporary data once the system or network operation has finished utilizing the local memory area.

Abstract: A network element includes one or more ports and a packet processor. The one or more ports are to transmit and receive packets over a network. The packet processor is to apply a plurality of rules to the packets, each rule specifying (i) expected values for each header field of a group of header fields of the packets, including, for a given header field in the group, at least a set of multiple expected values, (ii) a group ID associated with the set, and (iii) an action to be applied to the packets whose header fields match the expected values.

Abstract: A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.

Abstract: A system and method for controlling cooling in a server is provided. The method includes receiving one or more server indicators relating to a task to be executed by at least one component of the server. The method also includes determining an expected cooling demand for the at least one component based on the one or more server indicators. The method further includes adjusting a cooling amount provided by a cooling mechanism based on the expected cooling demand of the at least one component. Various embodiments are described herein.