Abstract: A beamforming element comprises an imprinting-shifting component configured to imprint an input signal onto a second beam to form an imprinted beam and adjust the optical phase of the imprinted beam; one or more multi-beam optical couplers configured to receive a phase-shifted imprinted beam and a first beam and form an interference beam from the combination thereof; and one or more optical-to-electrical converter components configured to receive an interference beam and generate an electrical signal based thereon that includes the beamforming time delay(s) and is frequency up/down-converted with respect to the input signal.

Abstract: A spine switch for a network switch comprises a support board that supports at least one first switch. The spine switch further includes a first set of connectors at a first edge of the support board that detachably connect to one or more first leaf switches to communicatively couple and decouple the at least one first switch from the one or more first leaf switches.

Abstract: A high performance mechanism for exporting peripheral services and offloads using Direct Memory Access (DMA) engine is presented. The DMA engine comprises a ring buffer, a DMA memory, and a DMA engine interface operatively coupled to the ring buffer and the DMA memory. The DMA engine interface is configured to retrieve, from the ring buffer, a first DMA request; extract first transfer instructions from the first DMA request; retrieve a first data corresponding to the first DMA request from the DMA memory; and execute the first DMA request using the first data based on at least the first transfer instructions.

Abstract: A processing device includes an interface and one or more processing circuits. The interface is to connect to a host processor. The one or more processing circuits are to receive from the host processor, via the interface, a notification specifying an operation for execution by the processing device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks, in response to the notification, to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation in accordance with the schedule.

Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.

Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.

Abstract: A network device includes a network interface, a host interface, and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host comprising a host processor running a client process. The processing circuitry is configured to receive packets belonging to a message having a message length, the message originating from a peer process, to identify, in at least some of the received packets, application-level information specifying the message length, to determine, based on the identified message length, that the packets of the message already received comprise only a portion of the message, and in response to determining that the client process benefits from receiving less than the entire message, to initiate reporting the packets of the message already received to the client process.

Abstract: A pluggable network interface device is provided comprising a split-shell housing having a shielded side portion that protects a side of a circuit substrate disposed in the split-shell housing. The split-shell housing comprises a first shell portion that covers a first side of the circuit substrate and a second shell portion that covers a second side of the circuit substrate that is arranged opposite the first side. The shielded side portion is inset from a width of the split-shell housing and offset a distance from an electrical interconnection end of the circuit substrate. The shielded side portion is arranged at least partially in a notch of the circuit substrate disposed at the electrical interconnection end of the circuit substrate.

Abstract: A memory device includes a memory cell and a controller. The memory cell includes: (a) an array of molecule chains, at least one molecule chain includes: (i) first and second binding sites positioned at first and second ends of the molecule chain, respectively, and (ii) a chain of one or more fullerene derivatives, chemically connecting between the first and second binding sites, (b) source and drain electrodes, electrically connected to the first and second binding sites, respectively, and configured to apply to the array a source-drain voltage (VSD) along a first axis, and (c) a gate electrode, configured to apply to the array a gate voltage (VG) along a second different axis. The controller is configured to perform a data storage operation in the memory cell by (i) applying to the gate electrode a signal for producing the VG, and (ii) applying the VSD between the source and drain electrodes.

Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.

Abstract: A method for communication includes partitioning local links in a subnetwork of a packet data network into at least first and second groups. For each local link that connects a first upper-tier switch to a first lower-tier switch in the subnetwork, a corresponding detour route is defined, passing through a first local link belonging to the first group from the first upper-tier switch to a second lower-tier switch, and from the second lower-tier switch over a second local link to a second upper-tier switch, and from the second upper-tier switch over a third local link belonging to the second group to the first lower-tier switch. Upon a failure of the local link connecting the first upper-tier switch to the first lower-tier switch, data packets arriving from the network at the first upper-tier switch are rerouted to pass via the corresponding detour route to the first lower-tier switch.

Abstract: API in conjunction with a bridge chip and first and second hosts having first and second memories respectively. The bridge chip connects the memories. The API comprises key identifier registration functionality to register a key identifier for each of plural computer processes performed by the first host, thereby to define plural key identifiers; and/or access control functionality to provide at least computer process P1 performed by the first host with access, typically via the bridge chip, to at least local memory buffer M2 residing in the second memory, typically after the access control functionality first validates that process P1 has a key identifier which has been registered, e.g., via the key identifier registration functionality. Typically, the access control functionality also prevents at least computer process P2, performed by the first host, which has not registered a key identifier, from accessing local memory buffer M2, e.g., via the bridge chip.

Abstract: High bandwidth (e.g., >100 GHz) modulators and methods of fabricating such are provided. An optical modulator comprises transmission lines configured to provide a respective radio frequency signal to a respective plurality of segmented capacitive loading electrodes; pluralities of segmented capacitive loading electrodes in electrical communication with a respective one of the transmission lines and in electrical communication with an interface layer of a semiconductor waveguide structure; and the semiconductor waveguide structure. The semiconductor waveguide structure is configured to modulate an optical signal propagating therethrough based at least in part on the respective radio frequency signal. The semiconductor waveguide structure comprises the interface layer, which (a) comprises a semiconductor material and (b) is configured such that an interface resistance of the modulator is ?4 Ohms.

Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.

Abstract: A device may include a printed circuit board (PCB), a plurality of surface-mount devices disposed on the PCB, wherein a thermal mass of each of the surface-mount devices ranges between a first thermal mass value and a second thermal mass value that is greater than the first thermal mass value, and a plurality of thermal capacitors disposed on the PCB, wherein a thermal mass of each of the thermal capacitors is equal to or greater than the first thermal mass value of the surface-mount devices.

Abstract: Methods, apparatuses, systems, computing devices, and/or the like are provided. An example system for heat dissipation may include a memory. The example system may also include a processor configured to receive at least one visual representation of at least a portion of the sky, determine, based on the at least one visual representation (e.g., using artificial intelligence), a mask distinguishing between clouded and cloudless portions of the sky, based on the mask, determine a direction in which to point a heat dissipation panel toward one or more aim portions of the sky, and generate a signal to cause one or more heat dissipation surfaces or panels to be moved (e.g., using a robotic arm) such that heat is radiated toward the one or more aim portions of the sky.

Abstract: A transceiver module for providing operational resilience is presented. The transceiver module is configured to receive first data via a first optical module in a first configuration of operation and detect, using an adapter that is operationally connected to the first optical module, an operational failure of the first optical module. In response to detecting the operational failure, the transceiver module is configured to switch, via the adapter, from the first configuration of operation to a second configuration of operation by: automatically engaging a second optical module; triggering the first data that was initially directed into a first input port of the first optical module to be directed into a second input port of the second optical module; and receiving the first data from a second output port of the second optical module.

Abstract: A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.

Abstract: A method using a memory and queue handling logic, including accessing a work control structure (WCS) configured “first-in-first-out” holding work control records (WCRs) each including a field defining work to be carried out and a completion indicator indicating whether the work has completed, and initially set to indicate that the work has not completed: upon fetching a work request (WR) for execution, pushing a WCR corresponding to the WR to the WCS, and: A) inspecting the WCR at a head of the WCS, B) when the completion indicator of the WCR at the head of the WCS indicates that the unit of work associated with the WCR at the head of the WCS has been completed, popping the WCR at the head of the WCS from the WCS, and reporting completion of the WCR at the head of the WCS to a host processor, and C) iteratively performing A, B, and C.

Abstract: Embodiments are disclosed for facilitating quantum computing over classical and quantum communication channels. An example system includes a network interface card (NIC) apparatus. The NIC apparatus includes an optical receiver, an embedded processor, and a network switch. The optical receiver is configured to receive qubit data via a first communication channel associated with quantum communication. The embedded processor is configured to convert the qubit data into binary bit data. The network switch is configured to output the binary bit data via a second communication channel associated with classical network communication.