Abstract: A first and a second flange assembly configured for facilitating uniform and laminar flow in a system are provided. The first flange assembly includes a first flange body configured to introduce a gas into a chamber. The first flange assembly includes a plurality of outlet tubes disposed on an interior surface of the first flange body and a plurality of inlet tubes disposed on an exterior surface of the first flange body and in fluid communication with the plurality of outlet tubes. The second flange assembly includes a second flange body configured to remove the gas from the chamber. The second flange assembly includes a plurality of through holes extending from an interior surface to an exterior surface of the second flange body and a plurality of exit tubes extending from the exterior surface of the second flange body and in fluid communication with the plurality of through holes.

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

Abstract: A method and system for analyzing Vertical-Cavity Surface-Emitting Lasers (VCSELs) on a wafer are provided. An illustrative method of is provided that includes: applying a stimulus to each of the plurality of VCSELs on the wafer; measuring, for each of the plurality of VCSELs, two or more VCSEL parameters responsive to the stimulus; correlating the measured two or more VCSEL parameters to define a value of a common performance characteristic; and identifying clusters of VCSELs having similar values of the common performance characteristic. The clusters of VCSELs may be determined to collectively meet or not meet an optical performance requirement defined for the VCSELs on the wafer.

Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

Abstract: A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i) a pattern of offsets to be accessed in the memory and (ii) a memory key representing a memory space to be accessed using the pattern, and to transfer the data in accordance with the request.

Abstract: A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.

Abstract: A method includes providing a library of hardware-agnostic packet-processing functions. A functional hardware-agnostic specification of a packet-processing pipeline is received from a user. The specification is defined in terms of one or more of the packet-processing functions drawn from the library. A hardware-specific design of the packet-processing pipeline, which is suited to given hardware, is derived from the specification.

Abstract: In one embodiment, a clock synchronization system includes clock circuitry to maintain a clock running at a clock frequency, a clock controller, and a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to apply the clock update commands to the clock, store a holdover frequency command to maintain the clock during a failure of the clock update commands, apply the holdover frequency command to the clock responsively to detecting the failure.

Abstract: In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the timer is activated responsively to a quantity of the multiple missing data packets.

Abstract: A network node includes a network adapter and a host. The network adapter is coupled to a communication network. The host includes a processor running a client process and a communication stack, and is configured to receive packets from the communication network, and classify the received packets into respective flows that are associated with respective chunks in a receive buffer, to distribute payloads of the received packets among the chunks so that payloads of packets classified to a given flow are stored in a given chunk assigned to the given flow, and to notify the communication stack of the payloads in the given chunk, for transferring the payloads in the given chunk to the client process.

Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

Abstract: Processes and devices for continuous compositional grading in photodetectors and electro-absorption modulators (EAM) are provided. An example photodetector includes a multi-layered structure comprising a collector region, an absorber region, a grading layer, and a peripheral layer, all aligned along a detection axis. The grading layer, positioned adjacent to the absorber region, includes multiple sub-layers that define a continuous compositional grading to facilitate smooth carrier transport and reduce recombination. Similarly, an example electro-absorption modulator (EAM) device includes a waveguide mesa formed on a semiconductor substrate, comprising a multi-quantum well (MQW) core layer, upper and lower near-core cladding layers, and upper and lower central cladding layers. The EAM device features both upper and lower grading layers, each positioned between the near-core cladding layers and the adjacent central cladding layers.

Abstract: Various embodiments of silicon photonic (SiP) chips are provided that are configured for backside or frontside optical fiber coupling. An SiP chip includes a photonic integrated circuit formed on a first surface of a first substrate. The photonic integrated circuit includes at least one optical component and at least one coupling element. The at least one optical component is configured to propagate an optical signal therethrough in a waveguide propagation direction that is substantially parallel to a plane defined by the first surface. The at least one coupling element is configured to couple an optical signal propagating along an optical path transverse to the waveguide propagation direction into the at least one optical component to enable the backside or frontside coupling of an optical fiber to the SiP chip.

Abstract: Electronic devices, electronic modules, and methods for manufacturing electronic devices and/or electronic modules are described herein. In some embodiments, the present invention may be directed to an electronic module that includes a pair of printed circuit boards (PCBs) and a capacitor positioned between the PCBs. Each of the PCBs may include a pair of vias configured to provide electrical connections through the PCB, and the capacitor may include a pair of pins. Each pin of the capacitor may be aligned with a via of one of the PCBs and a corresponding via of the other PCB such that each pin is configured to provide electrical connection between the two PCBs. Additionally, the pair of pins may be configured to support the PCBs with respect to each other.

Abstract: Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

Abstract: An optical interconnect device and the method of fabricating it are described. The device includes an in-plane laser cavity transmitting a light beam along a first direction, a Franz Keldysh (FK) optical modulator transmitting the light beam along the first direction, a mode-transfer module including a tapered structure disposed after the FK optical modulator along the first direction to enlarge the spot size of the light beam to match an external optical fiber and a universal coupler controlling the light direction. The tapered structure can be made linear or non-linear along the first direction. The universal coupler passes the laser light to an in-plane external optical fiber if the fiber is placed along the first direction, or it is a vertical coupler in the case that the external optical fiber is placed perpendicularly to the substrate surface. The coupler is coated with highly reflective material.

Abstract: An optoelectronic device (20) includes thin film structures (56) disposed on a semiconductor substrate (54) and patterned to define components of an integrated drive circuit, which is configured to generate a drive signal. A back end of line (BEOL) stack (42) of alternating metal layers (44, 46) and dielectric layers (50) is disposed over the thin film structures. The metal layers include a modulator layer (48), which contains a plasmonic waveguide (36, 99, 105) and a plurality of electrodes (30, 32, 34, 96, 98, 106), which apply a modulation to surface plasmons polaritons (SPPs) propagating in the plasmonic waveguide in response to the drive signal. A plurality of interconnect layers are patterned to connect the thin film structures to the electrodes.

Abstract: A device includes ports, a packet processor, and a memory management circuit. The ports communicate packets over a network. The packet processor processes the packets using queues. The memory management circuit maintains a shared buffer in a memory and adaptively allocates memory resources from the shared buffer to the queues, maintains in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by the queues, identifies, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool, and allocates memory resources to the identified queue from the shared-reserve memory pool.

Abstract: Methods, systems, and computer program products to generate a telemetry pipeline. In embodiments, the system includes a communication interface that receives one or more user-defined functions for the telemetry pipeline. The system also includes control logic that implements programmatically the one or more user-defined functions to collect telemetry data at a plurality of layers in the telemetry pipeline based on the one or more user-defined functions and calculate smart metrics at different layers of the plurality of layers in the telemetry pipeline. The smart metrics may be calculated at a layer closest to where associated telemetry data is collected.

Abstract: An optical interconnect device and the method of fabricating it are described. The device includes an in-plane laser cavity transmitting a light beam along a first direction, a Franz Keldysh (FK) optical modulator transmitting the light beam along the first direction, a mode-transfer module including a tapered structure disposed after the FK optical modulator along the first direction to enlarge the spot size of the light beam to match an external optical fiber and a universal coupler controlling the light direction. The tapered structure can be made linear or non-linear along the first direction. The universal coupler passes the laser light to an in-plane external optical fiber if the fiber is placed along the first direction, or it is a vertical coupler in the case that the external optical fiber is placed perpendicularly to the substrate surface. The coupler is coated with highly reflective material.