Abstract: In one aspect, a system for depositing a layer on a substrate is provided. The system includes a processing chamber, a gas injecting port, a gas distribution plate, and a plug. The gas injecting port is disposed upstream from the processing chamber. The gas distribution plate is disposed between the gas injecting port and the processing chamber, and includes an elongate planar body and an array of holes therein. The plug is sized to be received within one of the holes, and includes an orifice therethrough for permitting the passage of gas. The plug is capable of being removably secured to the gas distribution plate within one of the holes.
Abstract: A method of polishing a wafer is disclosed that includes determining a removal profile. The wafer is measured to determine a starting wafer profile and then the wafer is polished. The wafer is again measured after being polished to determine a polished wafer profile. The starting wafer profile and the polished wafer profile are compared to each other to determine the removal profile by computing the amount and shape of material removed from the first wafer during polishing.
March 13, 2013
September 18, 2014
MEMC ELECTRONIC MATERIALS, INC.
Sumeet S. Bhagavat, Khiam How Low, Ichiron Yoshimura, John Allen Pitney
Abstract: A gas distribution manifold for a chemical vapor deposition reactor includes a first gas distribution zone including a central gas port located in a central portion of the manifold. The manifold also includes a second gas distribution zone including at least two intermediate ports adjacent the central gas port. The manifold further includes a third gas distribution zone including at least two outer ports, each one of the outer ports spaced from the central gas port by one of the intermediate ports. The gas distribution manifold includes a fourth gas distribution zone comprising at least two edge ports, each edge port being spaced from the central outlet port by at least one of the intermediate and outer ports.
Abstract: An alignment system for aligning an ingot of semiconductor or solar-grade material is provided. The alignment system includes a mounting block for attachment to the ingot, an optical device for aligning a predetermined centerline of the ingot with a reference line, and adjustable supports configured for supporting the ingot on at least four support points and configured to adjust the position of the ingot. The mounting block is movable between a horizontal position and a vertical position.
Abstract: A method of aligning an ingot of semiconductor or solar-grade material with a mounting block includes supporting the ingot using adjustable supports, aligning a predetermined centerline of the ingot with a reference line using a laser, and attaching the mounting block to the ingot such that the predetermined centerline remains aligned with the reference line.
Abstract: A method and a system are described herein for applying etchant to edges of a plurality of wafers. The system includes a sump configured for holding etchant, a roller having an outer surface in fluid communication with the sump and configured to have etchant thereon, a wafer cassette configured to retain wafers positioned therein so that edges of the wafers are in contact with the roller. The cassette permits axial rotation of the wafers about an axis. A method of applying etchant to the edge of the wafer includes placing the wafer edge in contact with the roller and rotating the roller about a longitudinal axis of the roller. At least a portion of the roller contact an etchant contained in a sump during rotation so that etchant is applied to the wafer edge.
Abstract: Gas distribution units of fluidized bed reactors are configured to direct thermally decomposable compounds to the center portion of the reactor and away from the reactor wall to prevent deposition of material on the reactor wall and process for producing polycrystalline silicon product in a reactor that reduce the amount of silicon which deposits on the reactor wall.
Abstract: Production of polycrystalline silicon in substantially closed-loop processes and systems is disclosed. The processes and systems generally involve disproportionation of trichlorosilane to produce silane or dichlorosilane and thermal decomposition of silane or dichlorosilane to produce polycrystalline silicon.
Abstract: Systems and methods are disclosed for modulating the hydrostatic pressure in a double side wafer grinder having a pair of grinding wheels. The systems and methods use a processor to measure the amount of electrical current drawn by the grinding wheels. Pattern detection software is used to predict a grinding stage based on the measured electrical current. The hydrostatic pressure is changed by flow control valves at each stage to change the clamping pressure applied to the wafer and to thereby improve nanotopology in the processed wafer.
March 16, 2011
Date of Patent:
April 29, 2014
MEMC Electronic Materials, Inc.
Sumeet S. Bhagavat, Roland R. Vandamme, Tomomi Komura
Abstract: A method and apparatus for determining the fluidization quality of a fluidized bed reactor is disclosed. The method includes measuring pressure within the fluidized bed reactor to obtain a pressure signal. The pressure signal is then transformed using wavelet decomposition into higher-frequency details and lower-frequency approximations. The dominance of the various features is then calculated based on the energy of each feature in relation to the normalized wavelet energies. The fluidization quality of the fluidized bed reactor is then determined from a comparison over time of the calculated energies.
October 19, 2012
April 24, 2014
MEMC ELECTRONIC MATERIALS, INC.
Jia Wei Chew, Satish Bhusarapu, Keith E. Weatherford
Abstract: A feed assembly and method of use thereof of the present invention is used for the addition of a high pressure dopant such as arsenic into a silicon melt for CZ growth of semiconductor silicon crystals. The feed assembly includes a vessel-and-valve assembly for holding dopant, and a feed tube assembly, attached to the vessel-and-valve assembly for delivering dopant to a silicon melt. An actuator is connected to the feed tube assembly and a receiving tube for advancing and retracting the feed tube assembly to and from the surface of the silicon melt. A brake assembly is attached to the actuator and the receiving tube for restricting movement of the feed tube assembly and locking the feed tube assembly at a selected position.
Abstract: Pulling systems are disclosed for measuring the weight of an object coupled to a first end of a cable. The cable is routed over a pulley suspended from a load cell. The force exerted by the cable on the pulley is used to calculate the weight of the object. The second end of the cable is coupled to a drum which when rotated pulls the object by wrapping the cable around the drum. An arm is coupled to the pulley at one end and to a frame at another end. A path travelled by the cable between the pulley and the drum is substantially parallel to a longitudinal axis of the arm. Horizontal force components are transmitted by the arm to the frame and do not affect a force component measured by the load cell, thus increasing the accuracy of the calculated weight of the object.
Abstract: The present invention relates to a single crystal silicon ingot or wafer wherein the lateral incorporation effect of intrinsic point defects has been manipulated such that the formation of agglomerated intrinsic point defects and/or oxygen precipitate clusters in a ring extending radially inward from about the lateral surface of the ingot segment is limited.
Abstract: Apparatus and methods for wafer processes such as etching and chemical vapor deposition processes are disclosed. In some embodiments, the apparatus includes a susceptor and a ring disposed beneath the susceptor to influence a thickness of the deposited epitaxial layer.
Abstract: A susceptor for supporting a semiconductor wafer during an epitaxial chemical vapor deposition process, the susceptor defining a wafer diameter, the susceptor includes a substantially cylindrical body portion having opposing upper and lower surfaces. The body portion has a diameter larger than the wafer diameter. The susceptor includes a set of holes circumferentially disposed at a first susceptor diameter, the set of holes is evenly spaced with respect to adjacent holes and extending through the upper and lower surfaces in an area. The first susceptor diameter is larger than the wafer diameter, and holes are omitted along the first diameter in a predetermined orientation.
Abstract: A method of fabricating a semiconductor processing device includes providing a susceptor including a substantially cylindrical body portion having opposing upper and lower surfaces. The body portion has a diameter larger than a wafer diameter. The method also includes providing a set of holes circumferentially disposed at a first susceptor diameter, the set of holes being evenly spaced with respect to adjacent holes and extending through the upper and lower surfaces in an area. The first susceptor diameter is larger than the wafer diameter, and holes are omitted along the first diameter in a set of predetermined orientations.
Abstract: Controlling crystal growth in a crystal growing system is described. The crystal growing system includes a heated crucible including a semiconductor melt from which a monocrystalline ingot is grown according to a Czochralski and the ingot is grown on a seed crystal pulled from the melt. The method includes applying a cusped magnetic field to the melt by supplying an upper coil with a first direct current (IUDC) and supplying a lower coil with a second direct current (ILDC). The method also includes supplying the upper coil with a first alternating current (IUAC) and supplying the lower coil with a second alternating current (ILAC) to generate a time-varying magnetic field, wherein the time-varying magnetic field generates a pumping force in the semiconductor melt.
August 6, 2009
Date of Patent:
October 8, 2013
MEMC Electronic Materials, Inc.
Hariprasad Sreedharamurthy, Milind Kulkarni, Harold W. Korb
Abstract: A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures.
Abstract: Production of polycrystalline silicon in a substantially closed-loop process is disclosed. The processes generally include decomposition of trichlorosilane produced from metallurgical grade silicon.