Patents Assigned to MEMC Electronic Materials, Inc.
  • Patent number: 6600557
    Abstract: A process for detecting mechanical and mechanochemical defects in the surface or edge of a silicon wafer resulting from a wafer manufacturing process. The present process comprises treating a surface of the silicon wafer with an aqueous etch solution comprising hydrofluoric acid and an oxidizing agent, followed by optical inspection of the treated wafer surface prior to subjecting that surface to conventional mechanical or mechanochemical polishing. The present process affords the means by which to more efficient identify wafers having such defects, thus reducing wafer manufacturing time and cost.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: July 29, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Anca Stefanescu, Zhijian Pei, Henry F. Erk, Tom Doane
  • Patent number: 6599815
    Abstract: An apparatus and method for forming an epitaxial layer on and a denuded zone in a semiconductor wafer. A single chamber is used to form both the epitaxial layer and the denuded zone. The denuded zone is formed by heating the wafer in the chamber and then rapidly cooling the wafer while it is supported on an annular support whereby only a peripheral edge portion of the wafer is in contact with the support.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: July 29, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Charles Chiun-Chieh Yang
  • Publication number: 20030136961
    Abstract: A silicon wafer having a controlled oxygen precipitation behavior such that a denuded zone extending inward from the front surface and oxygen precipitates in the wafer bulk sufficient for intrinsic gettering purposes are ultimately formed. Specifically, prior to formation of the oxygen precipitates, the wafer bulk comprises dopant stabilized oxygen precipitate nucleation centers. The dopant is selected from a group consisting of nitrogen and carbon and the concentration of the dopant is sufficient to allow the oxygen precipitate nucleation centers to withstand thermal processing such as an epitaxial deposition process while maintaining the ability to dissolve any grown-in nucleation centers.
    Type: Application
    Filed: December 23, 2002
    Publication date: July 24, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Jeffrey L. Libbert, Richard J. Phillips, Milind Kulkarni, Mohsen Banan, Stephen J. Brunkhorst
  • Patent number: 6596095
    Abstract: A single crystal silicon wafer with a back surface free of an oxide seal and substantially free of a chemical vapor deposition process induced halo and an epitaxial silicon layer on the front surface, the epitaxial layer is characterized by an axially symmetric region extending radially outwardly from the central axis of the wafer toward the circumferential edge of the wafer having a substantially uniform resistivity, the radius of the axially symmetric region being at least about 80% of the length of the radius of the wafer.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: July 22, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Michael J. Ries, Charles Chiun-Chieh Yang, Robert W. Standley
  • Patent number: 6589332
    Abstract: A method and system for determining polycrystalline silicon chunk size for use with a Czochralski silicon growing process. Polycrystalline silicon chunks are arranged on a measuring background. A camera captures an image of the chunks. An image processor processes the image and determines the dimensions of the chunks based on the captured image. A size parameter associated with the chunks is determined.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: July 8, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: John D. Holder, Steven Joslin, Hariprasad Sreedharamurthy, John Lhamon
  • Patent number: 6586068
    Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies in the wafer. During the heat-treatment, the front and back surfaces of the wafer are each exposed to either a nitriding or non-nitriding gas. The wafer is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile determined in part by the gas that each surface is exposed to and in part by the cooling rate.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: July 1, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Publication number: 20030116081
    Abstract: A process for growing a single crystal silicon ingot having an axially symmetric region substantially free of agglomerated intrinsic point defects. The ingot is grown generally in accordance with the Czochralski method; however, the manner by which the ingot is cooled from the temperature of solidification to a temperature which is in excess of about 900° C. is controlled to allow for the diffusion of intrinsic point defects, such that agglomerated defects do not form in this axially symmetric region. Accordingly, the ratio v/G0 is allowed to vary axially within this region, due to changes in v or G0, between a minimum and maximum value by at least 5%.
    Type: Application
    Filed: September 30, 2002
    Publication date: June 26, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov, Paolo Mutti
  • Patent number: 6579779
    Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies in the wafer. During the heat-treatment, the front and back surfaces of the wafer are each exposed to either a nitriding gas or a non-nitriding gas. The front surface of the heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to further effect the vacancy concentration profile within the wafer.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: June 17, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Robert J. Falster
  • Patent number: 6579362
    Abstract: A heat shield assembly for use in a crystal puller has an outer reflector interposed between the ingot and the crucible as the ingot is pulled from the molten source material. A cooling shield is interposed between the ingot and the outer reflector whereby the cooling shield is exposed to heat radiated from the ingot for increasing the rate at which the ingot is cooled, thereby increasing the axial temperature gradient of the ingot. In a further embodiment, an inner shield panel is disposed generally intermediate the cooling shield and the ingot in radially spaced relationship with the cooling shield and is constructed of a material substantially transparent to radiant heat from the ingot.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: June 17, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Lee W. Ferry, Richard G. Schrenker, Mohsen Banan
  • Publication number: 20030104680
    Abstract: A process of removing metallic impurities from a polished boron-doped silicon wafer comprising forming an oxide layer on the polished wafer that is thicker than a typical native oxide layer so that the oxide layer has a greater gettering capacity than a native oxide layer gettering capacity and then annealing the wafer at a temperature of at least about 75° C. for at least about 30 seconds to decrease the concentration of the metallic impurity in the interior of the silicon wafer and increase the concentration of the metallic impurity on the polished surface of the silicon wafer and in the oxide layer. Preferably, the annealed silicon wafer is cleaned to remove the oxide layer and to remove the metallic impurity from the polished surface of the silicon wafer. By repeatedly creating an oxide layer and annealing the wafer, the wafer can be made substantially free of metallic impurities.
    Type: Application
    Filed: November 13, 2002
    Publication date: June 5, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Andrei D. Stefanescu, Leonard O. Rosik, Tina L. Gardner
  • Publication number: 20030101924
    Abstract: A process for preparing a silicon melt in a crucible for use in growing a single crystal silicon ingot by the Czochralski method. The crucible is first loaded with chunk polycrystalline silicon and heated to partially melt the load. Granular polycrystalline silicon is then fed onto the exposed unmelted chunk polycrystalline silicon to complete the charge of silicon in the crucible. The granular polycrystalline silicon is intermittently delivered using a plurality of alternating on-periods and off-periods. During each on-period, granular polycrystalline silicon is flowed through a feed device that directs the granular polycrystalline silicon onto the unmelted chunk polycrystalline silicon. During each off-period, the flow of the granular polycrystalline silicon is interrupted. The loaded chunk polycrystalline silicon and the fed granular polycrystalline silicon are melted to form the silicon melt.
    Type: Application
    Filed: November 15, 2001
    Publication date: June 5, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventor: John Davis Holder
  • Patent number: 6565649
    Abstract: The present invention is directed to an epitaxial wafer comprising a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: May 20, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule′Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
  • Patent number: 6562123
    Abstract: A process for growing single crystal silicon ingots of which portions are substantially free of agglomerated intrinsic point defects. An ingot is grown generally in accordance with the Czochralski method. A first portion of the ingot cools to a temperature which is less than a temperature TA at which agglomeration of intrinsic point defects in the ingot occurs during the time the ingot is being grown, while a second portion remains at a temperature above TA. The second portion of the ingot is subsequently maintained at a temperature above TA to produce a portion which is substantially free of agglomerated intrinsic point defects.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: May 13, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Harold W. Korb
  • Publication number: 20030079673
    Abstract: The present invention provides for a process for preparing a single crystal silicon ingot by the Czochralski method. The process comprises selecting a seed crystal for Czochralski growth wherein the seed crystal comprises vacancy dominated single crystal silicon.
    Type: Application
    Filed: October 28, 2002
    Publication date: May 1, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Hariprasad Sreedharamurthy, Mohsen Banan
  • Patent number: 6554898
    Abstract: A crystal puller for growing monocrystalline silicon ingots includes first and second electrical resistance heaters in the crystal puller in longitudinal, closely spaced relationship with each other to radiate heat toward the ingot as the ingot is pulled upward within the housing. An adapter mounting the heaters may also be provided for adapting existing crystal pullers to incorporate the heaters.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: April 29, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Zheng Lu, Mohsen Banan, Ying Tao, Lee Ferry, Carl F. Cherko
  • Patent number: 6555194
    Abstract: The present invention is directed to a process for producing a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects. The process including growing a single crystal silicon ingot from molten silicon, and as part of the growth process, controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C., and (iii) a cooling rate of the crystal from a solidification temperature to about 1,050° C., in order to cause the formation of an axially symmetrical segment which is substantially free of agglomerated intrinsic point defects.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: April 29, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert A. Falster, Joseph C. Holzer, Marco Cornara, Daniela Gambaro, Massimiliano Olmo, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
  • Publication number: 20030077128
    Abstract: A granular semiconductor material transport system capable of continuous, non-contaminating transfer of granular semiconductor material from a large source vessel to a smaller and more manageable target vessel. Movement of the granular material is induced by flowing transfer fluid. The system includes a source vessel, a feed tube, a process vessel, a target vessel and a vacuum source, or mover. The source vessel contains a bulk supply of granular material to be transported. A feed tube received within the source vessel transfers the granular material entrained in a transfer fluid from the source vessel to the process vessel. The process vessel separates the granular material from any dust particles and deposits the granular material in the more manageable target vessel. The vacuum source sealably connects to the process vessel to evacuate the process vessel to set the granular polysilicon in motion within the system.
    Type: Application
    Filed: October 23, 2001
    Publication date: April 24, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Dick S. Williams, Howard VanBooven, Jimmy D. Kurz, Timothy J. Kulage
  • Publication number: 20030061985
    Abstract: A single crystal silicon ingot having a constant diameter portion that contains arsenic dopant atoms at a concentration which results in the silicon having a resistivity that is less than about 0.0025 &OHgr;·cm, and wafers sliced therefrom. The present invention is also directed to a method of doping a silicon melt so that the foregoing ingot may be produced. Specifically, the method entails introducing arsenic dopant below the surface of a silicon melt, rather than on the surface, using a dopant feeder that is at least partially submersed in the silicon melt.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 3, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Milind Kulkarni, Mohsen Banan, Christopher V. Luers
  • Publication number: 20030064902
    Abstract: A process for forming a semiconductor wafer which is single side polished improves nanotopography and flatness of the polished wafer. The process reduces the effect of back side surface features, such as edge ring phenomena and back side laser marks, on nanotopography and local site flatness, thereby improving oxide layer uniformity for chemical/mechanical planarization (CMP) processing, and flatness on the polished front side of the wafer after polishing. The wafer is mounted on a polishing block by wax so as to minimize transfer of imperfections in the wax to the front side of the wafer. In particular, the wafer is retained in a centered position on the polishing block. Moreover, the wafer is mounted at atmospheric pressure while still removing air bubbles from the wax.
    Type: Application
    Filed: October 3, 2001
    Publication date: April 3, 2003
    Applicant: MEMC Electronic Materials Inc.
    Inventors: Kan-Yin Ng, James Jose, Stephen Hensiek, Peter Albrecht
  • Patent number: 6537655
    Abstract: This invention is directed to a novel a single crystal silicon wafer. In one embodiment, this wafer comprises: (a) two major generally parallel surfaces (i.e., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: March 25, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Gregory M. Wilson, Jon A. Rossi, Charles C. Yang