Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Abstract: A heteroepitaxial semiconductor wafer includes a heteroepitaxial layer forming the front surface of the wafer that includes a secondary material having a different crystal structure than that of the wafer primary material. The heteroepitaxial layer is substantially free of defects. A surface layer includes the primary material and is free of the secondary material. The surface layer borders the heteroepitaxial layer. A bulk layer includes the primary material and is free of the secondary material. The bulk layer borders the surface layer and extends through the central plane. An SOI wafer and a method of making wafers is disclosed.

Abstract: A high-purity semiconductor grade granular silicon composition and methods for making the same are disclosed. Commercial quantities of the granular silicon can be produced by depositing silicon on silicon seeds in a first chemical vapor deposition (CVD)reactor, thereby growing the seeds into larger secondary seeds. Additional silicon is deposited on the secondary seeds in a second CVD reactor. Dust is reduced in a third reactor. The methods disclosed herein can be used to achieve higher throughput and better yield than conventional practices.

Abstract: A wafer boat for use in heat treatment of semiconductor wafers in a vertical furnace comprises support rods extending generally vertically when the wafer boat is placed in the vertical furnace. Fingers are supported by and extend along vertical extent of the support rods. Wafer holder platforms are adapted to be supported by groups of fingers lying in generally different common horizontal planes. The fingers are adapted to underlie the wafer holder platforms and support the platforms at the support locations. The fingers and wafer holder platforms each have a respective first overall maximum thickness. The support location of at least one of the fingers and the wafer holder platforms have a second maximum thickness less than the first overall maximum thickness.

Abstract: A process for nucleating and growing oxygen precipitates in a silicon wafer, including subjecting a wafer having a non-uniform concentration of crystal lattice vacancies with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer to a non-isothermal heat treatment to form of a denuded zone in the surface layer and to cause the formation and stabilization of oxygen precipitates having an effective radial size 0.5 nm to 30 nm in the bulk layer. The process optionally includes subjecting the stabilized wafer to a high temperature thermal process (e.g. epitaxial deposition, rapid thermal oxidation, rapid thermal nitridation and etc.) at temperatures in the range of 1000 OC to 1275 OC without causing the dissolution of the stabilized oxygen precipitates.

Abstract: A wafer carrier for retaining at least one semiconductor wafer in a processing apparatus during a processing operation which removes wafer material by at least one of abrading and chemical reaction. The processing apparatus is adapted for removing wafer material from a front side and a back side of each wafer simultaneously. The carrier includes a plate including wafer contaminating material and having an opening and a thickness. An insert has a thickness and is disposed in the opening for receiving at least one wafer and engaging a peripheral edge of the wafer to hold the wafer as the carrier rotates. The thickness of the insert is significantly greater than the thickness of the plate to inhibit removal of material from the plate and thereby inhibit bulk metal contamination of the wafer.

Abstract: The present invention is directed to a process for reclaiming for reuse a single crystal silicon wafer removed from an aborted semiconductor device fabrication process. The process includes (a) subjecting the wafer to an oxide growth step to form an oxide layer having a thickness greater than 2 nanometers, (b) thinning the wafer by removing material from substantially the entire front surface to provide a thinned wafer having a thinned precipitate free zone, and (c) polishing the front surface of the thinned wafer to a specular finish.

Abstract: A single crystal silicon wafer comprising a front surface, a back surface, a lateral surface joining the front and back surfaces, a central axis perpendicular to the front and back surfaces, and a segment which is axially symmetric about the central axis extending substantially from the front surface to the back surface in which crystal lattice vacancies are the predominant intrinsic point defect, the segment having a radial width of at least about 25% of the radius and containing agglomerated vacancy defects and a residual concentration of crystal lattice vacancies wherein (i) the agglomerated vacancy defects have a radius of less than about 70 nm and (ii) the residual concentration of crystal lattice vacancy intrinsic point defects is less than the threshold concentration at which uncontrolled oxygen precipitation occurs upon subjecting the wafer to an oxygen precipitation heat treatment.

Abstract: The present invention provides a methods and system for producing semiconductor grade single crystals that are substantially free of undesirable agglomerated defects. A vacancy/interstial (V/I) boundary simulator analyzes various melt-solid interface shapes to predict a corresponding V/I transition curve for each of the various melt-solid interface shapes. A target melt-solid interface shape corresponding to a substantially flat V/I curve is identified for each of a plurality of axial positions along the length of the crystal. Target operating parameters to achieve each of the identified melt-solid interface shapes are stored in a melt-solid interfaced shape profile. A control system is responsive to the stored profile to generate one or more control signals to control one or more output devices such that the melt-solid interfaced shape substantially follows the target shapes as defined by the profile during crystal growth.

Abstract: A melter assembly supplies a charge of molten source material to a crystal forming apparatus for use in forming crystalline bodies. The melter assembly comprises a housing and a crucible located in the housing. A heater is disposed relative to the crucible for melting solid source material received in the crucible. The crucible has a nozzle to control the flow of molten source material such that a directed flow of molten source material can be supplied to the crystal forming apparatus at a selected flow rate.

Abstract: A method of charging a crystal forming apparatus with molten source material is provided. The method includes the steps of positioning a melter assembly relative to the crystal forming apparatus for delivering molten silicon to a crucible of the apparatus. An upper heating coil in the melter assembly is operated to melt source material in a melting crucible. A lower heating coil in the melter assembly is operated to allow molten source material to flow through an orifice of the melter assembly to deliver a stream of molten source material to the crucible of the crystal forming apparatus. The invention is also directed to a method of charging a crystal puller with molten silicon including the step of removing an upper housing of the crystal puller defining a pulling chamber from a lower housing of the crystal puller defining a growth chamber and attaching the lower housing in place of the upper housing.

Abstract: A method of servicing multiple crystal forming apparatus with a single melter assembly is provided. The method includes the steps of positioning the melter assembly relative to a first crystal forming apparatus for delivering molten silicon to a crucible of the first apparatus. A heater in the melter assembly is operated to melt source material in a melting crucible. A stream of molten source material is delivered from the melter assembly to the first crystal forming apparatus. The melter assembly is positioned relative to a second crystal forming apparatus for delivering molten silicon to a crucible of the second apparatus. A stream of molten source material is transferred from the melter assembly to the second crystal forming apparatus.

Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Abstract: A method and apparatus for controlling the quenching rate of a monocrystalline ingot pulled from a melt by adjusting one or more post growth processing parameter. A temperature model generates a temperature profile that represents the surface temperature along the length of the ingot at the instant it is pulled from the melt. A first temperature at a particular location along the length of the crystal is determined from the temperature profile. A temperature sensor senses a second temperature at the same particular location. A PLC calculates a quenching rate of the crystal as a function of the first temperature and the second temperature. The PLC generates an error between a target quenching rate and a calculated quenching rate, and one or more post growth process parameters are adjusted as function of the error signal to optimize the quenching rate.

Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, having an axially symmetric vacancy dominated region and an axially symmetric silicon self-interstitial dominated region. Both the vacancy dominated and the silicon self-interstitial dominated regions are substantially free of agglomerated intrinsic point defects. The vacancy dominated region has a radial width of at least 15 mm and/or includes the central axis and the silicon self-interstitial dominated region is annular in shape and extends radially outward from the vacancy dominated region to the peripheral edge of the ingot or wafer. In ingot form, the axially symmetric regions have an axial length which is at least 20% of the length of the constant diameter portion of the ingot.

Abstract: A wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer. In addition, the front surface of the wafer has an epitaxial layer, having a thickness of less than about 2.0 çm, deposited thereon. A process comprises heating a surface of a wafer starting material to remove a silicon oxide layer from the surface and depositing an epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant, and the wafer is cooled at a rate of at least about 10C./sec.

Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has a non-uniform distribution of stabilized oxygen precipitate nucleation centers therein. Specifically, the peak concentration is located in the wafer bulk and a precipitate-free zone extends inward from a surface.

Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process comprises controlling growth conditions, such as growth velocity, v, instantaneous axial temperature gradient, G0, and the cooling rate, within a range of temperatures at which silicon self-interstitials are mobile, in order to prevent the formation of these agglomerated defects. In ingot form, the axially symmetric region has a width, as measured from the circumferential edge of the ingot radially toward the central axis, which is at least about 30% the length of the radius of the ingot. The axially symmetric region additionally has a length, as measured along the central axis, which is at least about 20% the length of the constant diameter portion of the ingot.

Abstract: A fluid sealing system is provided for use in a crystal puller for growing a monocrystalline ingot. The crystal puller has a housing, a fluid flow path contained in the housing, and a fluid passage through a wall of the housing for passage of fluid. The fluid sealing system includes a fluid connector head adapted for connection to the fluid passage and to the fluid flow path to establish fluid communication between the fluid flow path and the outside of the housing. The head has a port adapted for fluid communication with the fluid passage through the wall of the housing. First and second seals around the port are adapted for sealing engagement with the head. A space is defined generally between the first and second seals, and a leak detector is arranged to monitor the space for detecting fluid leakage past at least one of the seals.

Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.