Abstract: This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure.

Abstract: A system for measuring the weight of an object while pulling the object upward includes a puller having a frame and a cable having a first end coupled to the object and a second end engaging a second cylinder. At least a portion of the cable engages the outer circumferential surface of a first cylinder and the second cylinder. The apparatus also includes an upper arm and an actuator. A force measurement device is coupled to the first cylinder and to the upper arm and measures the weight of the object. The actuator is operable to lower and raise the weight measurement device and the first cylinder. In some embodiments, the position of the cable with respect to the frame may be adjusted by a dampening system or a bushing.

Abstract: Methods for producing silane by reacting a hydride and a halosilane are disclosed. Some embodiments involve use of a column which is not mechanically agitated and in which reactants may be introduced in a counter-current arrangement. Some embodiments involve use of a baffled column which has multiple reaction zones.

Abstract: Systems and computer-readable media having computer-executable components are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.

Abstract: Systems and methods are provided for controlling silicon rod temperature. In one example, a method of controlling a surface temperature of at least one silicon rod in a chemical vapor deposition (CVD) reactor during a CVD process is presented. The method includes determining an electrical resistance of the at least one silicon rod, comparing the resistance to a set point to determine a difference, and controlling a power supply to control a power output coupled to the at least one silicon rod to minimize an absolute value of the difference.

Abstract: The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: A silicon-on-insulator or bonded wafer includes an upper portion having a trapezoid shape in cross-section and a lower portion having an outer peripheral edge having a curved shape.

Abstract: The present disclosure relates to processes and systems for purifying technical grade trichlorosilane and/or technical grade silicon tetrachloride into electronic grade trichlorosilane and/or electronic grade silicon tetrachloride.

Abstract: Methods for holding a workpiece with a hydrostatic pad are disclosed herein. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.

Abstract: A support for a semiconductor wafer includes a plate having a support surface for supporting the wafer and a recessed surface spaced from the support surface and spaced from the wafer. A plurality of holes extends from the recessed surface, and the support surface is free of holes to inhibit contamination of the wafer.

Abstract: A wafer boat for a semiconductor wafer includes vertical rods, fingers supported by the vertical rods, and plates supported by the fingers. The plate has a support surface for supporting the wafer and a recessed surface spaced from the support surface and spaced from the wafer. A plurality of holes extends from the recessed surface, and the support surface is free of holes to inhibit contamination of the wafer.

Abstract: Processes for preparing a single crystal silicon ingot are disclosed. In certain embodiments, the processes involve controlling (1) a growth velocity, v, of the ingot as well as (2) an average axial temperature gradient, G, a corrected average axial temperature gradient, Gcorrected, or an effective average axial temperature gradient, Geffective, during the growth of at least a segment of the constant diameter portion of the ingot.

Abstract: A wafer polishing apparatus has a base and a turntable having a polishing pad thereon and mounted on the base for rotation of the turntable and polishing pad relative to the base about an axis perpendicular to the turntable and polishing pad. The polishing pad includes a work surface engageable with a front surface of a wafer for polishing the front surface of the wafer. A drive mechanism is mounted on the base for imparting rotational motion about an axis substantially parallel to the axis of the turntable. A polishing head is connected to the drive mechanism for driving rotation of the polishing head. The polishing head has a pressure plate adapted to hold the wafer for engaging the front surface of the wafer with the work surface of the polishing pad. The pressure plate has a generally planar position and is selectively movable from the planar position to a convex position and to a concave position.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: A wafer holder for holding a semiconductor wafer during a thermal wafer treatment process. The wafer holder includes at least three wafer supports. Each wafer support includes an upright shaft and a plurality of flexible fibers supported by the shaft in positions such that at least some of the fibers engage the semiconductor wafer when the wafer rests on the wafer supports.

Abstract: Production of polycrystalline silicon in a substantially closed-loop process is disclosed. The processes generally include decomposition of trichlorosilane produced from metallurgical grade silicon.

Abstract: Production of polycrystalline silicon in a substantially closed-loop process is disclosed. The processes generally include decomposition of trichlorosilane produced from metallurgical grade silicon.

Abstract: Methods are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.

Abstract: A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.