Patents Assigned to MEMC Electronic Materials
  • Nitrogen-doped silicon substantially free of oxidation induced stacking faults
    Patent number: 7182809
    Abstract: A single crystal silicon, ingot or wafer form, which contains an axially symmetric region in which vacancies are the predominant intrinsic point defect, is substantially free of oxidation induced stacking faults and is nitrogen doped to stabilize oxygen precipitation nuclei therein, and a process for the preparation thereof.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: February 27, 2007
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Hiroyo Haga, Takaaki Aoshima, Mohsen Banan
  • High resistivity silicon structure and a process for the preparation thereof
    Publication number: 20060263967
    Abstract: The present invention generally relates to a high resistivity CZ silicon wafer, or a high resistivity silicon structure derived therefrom, and a process for the preparation thereof. In particular, the high resistivity silicon structure comprises a large diameter CZ silicon wafer as the substrate thereof, wherein the resistivity of the substrate wafer is decoupled from the concentration of acceptor atoms (e.g., boron) therein, the resistivity of the substrate being substantially greater than the resistivity as calculated based on the concentration of said acceptor atoms therein.
    Type: Application
    Filed: May 18, 2006
    Publication date: November 23, 2006
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Robert Falster, Vladimir Voronkov, Galina Voronkova, Anna Batunina
  • Semiconductor wafer, polishing apparatus and method
    Patent number: 7137874
    Abstract: A wafer polishing apparatus for polishing a semiconductor wafer. The polisher comprises a base (23), a turntable (27), a polishing pad (29) and a drive mechanism (45) for driven rotation of a polishing head (63). The polishing head is adapted to hold at least one wafer (35) for engaging a front surface of the wafer with a work surface of the polishing pad. A spherical bearing assembly (75) mounts the polishing head (63) on the drive mechanism for pivoting of the polishing head about a gimbal point (p) lying no higher than the work surface when the polishing head holds the wafer in engagement with the polishing pad. This pivoting allowing the plane of the front surface of the wafer to continuously align itself to equalize polishing pressure over the front surface of the wafer, while rotation of the polishing head is driven by the driving mechanism.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: November 21, 2006
    Assignee: MEMC Electronic Materials, SpA
    Inventors: Ezio Bovio, Paride Corbellini, Marco Morganti, Giovanni Negri, Peter D. Albrecht
  • Method for controlling of thermal donor formation in high resistivity CZ silicon
    Patent number: 7135351
    Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: November 14, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Martin J. Binns, Robert J. Falster, Jeffrey L. Libbert
  • Single crystal silicon ingot having a high arsenic concentration
    Patent number: 7132091
    Abstract: A single crystal silicon ingot having a constant diameter portion that contains arsenic dopant atoms at a concentration which results in the silicon having a resistivity that is less than about 0.003 ?·cm.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: November 7, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Milind Kulkarni, Mohsen Banan, Christopher V. Luers
  • Process for preparing single crystal silicon using crucible rotation to control temperature gradient
    Patent number: 7125450
    Abstract: The present invention is directed to a process for preparing single crystal silicon, in ingot or wafer form, wherein crucible rotation is utilized to control the average axial temperature gradient in the crystal, G0, as a function of radius (i.e., G0(r)), particularly at or near the central axis. Additionally, crucible rotation modulation is utilized to obtain an axially uniform oxygen content therein.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: October 24, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Zheng Lu, Steven L. Kimbel, Ying Tao
  • Modified susceptor for barrel reactor
    Publication number: 20060231035
    Abstract: A susceptor for supporting wafers during an chemical vapor deposition process. The susceptor has recesses and orifices disposed in the recesses extending to a central passage of the susceptor. The susceptor has exhaust openings disposed in the top of the susceptor to allow gas from the central passage of the susceptor to exit out the openings. A baffle plate covers the exhaust openings and a vertical space is created between the baffle plate and the top of the susceptor to allow gas to exit from the central passage to outside the susceptor. The bottom of the susceptor also has exhaust openings disposed therein. These openings allow gas from the central passage to exit the susceptor.
    Type: Application
    Filed: April 15, 2005
    Publication date: October 19, 2006
    Applicant: MEMC Electronic Materials, Inc.
    Inventor: Lance Hellwig
  • Method for the production of low defect density silicon
    Patent number: 7105050
    Abstract: A process for the preparation of a silicon single ingot in accordance with the Czochralski method. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C. to initially produce in the constant diameter portion of the ingot a series of predominant intrinsic point defects including vacancy dominated regions and silicon self interstitial dominated regions, alternating along the axis, and cooling the regions from the temperature of solidification at a rate which allows silicon self-interstitial atoms to diffuse radially to the lateral surface and to diffuse axially to vacancy dominated regions to reduce the concentration intrinsic point defects in each region.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: September 12, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Vladimir V. Voronkov, Robert J. Falster, Mohsen Banan
  • Single crystal silicon wafer having an epitaxial layer substantially free from grown-in defects
    Patent number: 7097718
    Abstract: Epitaxial wafers comprising a single crystal silicon substrate comprising agglomerated vacancy defects and having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated intrinsic point defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: August 29, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
  • Process for metallic contamination reduction in silicon wafers
    Patent number: 7084048
    Abstract: A process for removing a contaminant selected from among copper, nickel, and a combination thereof from a silicon wafer having a surface and an interior. The process comprises cooling the silicon wafer in a controlled atmosphere from a temperature at or above an oxidation initiation temperature and initiating a flow of an oxygen-containing atmosphere at said oxidation initiation temperature to create an oxidizing ambient around the silicon wafer surface to form an oxide layer on the silicon wafer surface and a strain layer at an interface between the oxide layer and the silicon wafer interior. The cooling of the wafer is also controlled to permit diffusion of atoms of the contaminant from the silicon wafer interior to the strain layer. Then the silicon wafer is then cleaned to remove the oxide layer and the strain layer, thereby removing said contaminant having diffused to the strain layer.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: August 1, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Larry W. Shive, Brian L. Gilmore
  • Electromagnetic pumping of liquid silicon in a crystal growing process
    Publication number: 20060144320
    Abstract: A method and system for use in combination with a crystal growing apparatus for growing a monocrystalline ingot according to a Czochralski process. The crystal growing apparatus has a heated crucible including a semiconductor melt from which the ingot is pulled. The ingot is grown on a seed crystal pulled from the melt. A time varying external magnetic field is imposed on the melt during pulling of the ingot. The magnetic field is selectively adjusted to produce pumping forces in the melt to control a melt flow velocity while the ingot is being pulled from the melt.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Applicant: MEMC Electronic Materials, Inc.
    Inventor: Harold Korb
  • Controlling melt-solid interface shape of a growing silicon crystal using a variable magnetic field
    Publication number: 20060144321
    Abstract: Methods and system for controlling crystal growth in a Czochralski crystal growing apparatus. A magnetic field is applied within the crystal growing apparatus and varied to control a shape of the melt-solid interface where the ingot is being pulled from the melt. The shape of the melt-solid interface is formed to a desired shape in response to the varied magnetic field as a function of a length of the ingot.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Applicant: MEMC Electronic Materials, Inc.
    Inventor: Zheng Lu
  • Process for producing silicon on insulator structure having intrinsic gettering by ion implantation
    Patent number: 7071080
    Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: July 4, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Jeffrey L. Libbert
  • Internally gettered heteroepitaxial semiconductor wafers and methods of manufacturing such wafers
    Publication number: 20060138601
    Abstract: A heteroepitaxial semiconductor wafer includes a heteroepitaxial layer forming the front surface of the wafer that includes a secondary material having a different crystal structure than that of the wafer primary material. The heteroepitaxial layer is substantially free of defects. A surface layer includes the primary material and is free of the secondary material. The surface layer borders the heteroepitaxial layer. A bulk layer includes the primary material and is free of the secondary material. The bulk layer borders the surface layer and extends through the central plane. An SOI wafer and a method of making wafers is disclosed.
    Type: Application
    Filed: April 13, 2005
    Publication date: June 29, 2006
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Michael Seacrist, Gregory Wilson, Robert Standley
  • High purity granular silicon and method of manufacturing the same
    Publication number: 20060105105
    Abstract: A high-purity semiconductor grade granular silicon composition and methods for making the same are disclosed. Commercial quantities of the granular silicon can be produced by depositing silicon on silicon seeds in a first chemical vapor deposition (CVD)reactor, thereby growing the seeds into larger secondary seeds. Additional silicon is deposited on the secondary seeds in a second CVD reactor. Dust is reduced in a third reactor. The methods disclosed herein can be used to achieve higher throughput and better yield than conventional practices.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 18, 2006
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Jameel Ibrahim, Melinda Ivey, Timothy Truong
  • Semiconductor wafer boat for a vertical furnace
    Patent number: 7033168
    Abstract: A wafer boat for use in heat treatment of semiconductor wafers in a vertical furnace comprises support rods extending generally vertically when the wafer boat is placed in the vertical furnace. Fingers are supported by and extend along vertical extent of the support rods. Wafer holder platforms are adapted to be supported by groups of fingers lying in generally different common horizontal planes. The fingers are adapted to underlie the wafer holder platforms and support the platforms at the support locations. The fingers and wafer holder platforms each have a respective first overall maximum thickness. The support location of at least one of the fingers and the wafer holder platforms have a second maximum thickness less than the first overall maximum thickness.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: April 25, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Puneet Gupta, Larry W. Shive, Brian L. Gilmore
  • Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates
    Publication number: 20060075960
    Abstract: A process for nucleating and growing oxygen precipitates in a silicon wafer, including subjecting a wafer having a non-uniform concentration of crystal lattice vacancies with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer to a non-isothermal heat treatment to form of a denuded zone in the surface layer and to cause the formation and stabilization of oxygen precipitates having an effective radial size 0.5 nm to 30 nm in the bulk layer. The process optionally includes subjecting the stabilized wafer to a high temperature thermal process (e.g. epitaxial deposition, rapid thermal oxidation, rapid thermal nitridation and etc.) at temperatures in the range of 1000 OC to 1275 OC without causing the dissolution of the stabilized oxygen precipitates.
    Type: Application
    Filed: November 21, 2005
    Publication date: April 13, 2006
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Marco Borgini, Daniela Gambaro, Marco Ravani, Michael Ries, Laura Sacchetti, Robert Standley, Robert Falster, Mark Stinson
  • Process for reclaiming semiconductor wafers and reclaimed wafers
    Patent number: 7008874
    Abstract: The present invention is directed to a process for reclaiming for reuse a single crystal silicon wafer removed from an aborted semiconductor device fabrication process. The process includes (a) subjecting the wafer to an oxide growth step to form an oxide layer having a thickness greater than 2 nanometers, (b) thinning the wafer by removing material from substantially the entire front surface to provide a thinned wafer having a thinned precipitate free zone, and (c) polishing the front surface of the thinned wafer to a specular finish.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: March 7, 2006
    Assignee: MEMC Electronics Materials, Inc.
    Inventor: Robert J. Falster
  • Wafer carrier
    Patent number: 7008308
    Abstract: A wafer carrier for retaining at least one semiconductor wafer in a processing apparatus during a processing operation which removes wafer material by at least one of abrading and chemical reaction. The processing apparatus is adapted for removing wafer material from a front side and a back side of each wafer simultaneously. The carrier includes a plate including wafer contaminating material and having an opening and a thickness. An insert has a thickness and is disposed in the opening for receiving at least one wafer and engaging a peripheral edge of the wafer to hold the wafer as the carrier rotates. The thickness of the insert is significantly greater than the thickness of the plate to inhibit removal of material from the plate and thereby inhibit bulk metal contamination of the wafer.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: March 7, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Mick Bjelopavlic, Alexis Grabbe, Michele Haler, Tracy M. Ragan
  • Single crystal silicon having improved gate oxide integrity
    Patent number: 6986925
    Abstract: A single crystal silicon wafer comprising a front surface, a back surface, a lateral surface joining the front and back surfaces, a central axis perpendicular to the front and back surfaces, and a segment which is axially symmetric about the central axis extending substantially from the front surface to the back surface in which crystal lattice vacancies are the predominant intrinsic point defect, the segment having a radial width of at least about 25% of the radius and containing agglomerated vacancy defects and a residual concentration of crystal lattice vacancies wherein (i) the agglomerated vacancy defects have a radius of less than about 70 nm and (ii) the residual concentration of crystal lattice vacancy intrinsic point defects is less than the threshold concentration at which uncontrolled oxygen precipitation occurs upon subjecting the wafer to an oxygen precipitation heat treatment.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: January 17, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Paolo Mutti, Francesco Bonoli