Patents Assigned to MEMC
  • Patent number: 6120350
    Abstract: A pad shaping tool for shaping a polishing pad. The tool includes a disk having a first side and a second side and at least two discontinuous pad shaping surfaces located in spaced apart positions relative to each other on the first side of the disk. The pad shaping surfaces are simultaneously engageable with a polishing surface of the polishing pad for shaping the polishing surface as the pad rotates relative to the tool to change a cross sectional profile of the polishing surface from a curved shape to a flatter shape. A process for reconditioning the polishing pad on a rotatable platform of a wafer polishing machine includes the steps of engaging the pad shaping tool with the polishing surface of the pad such that at least two discontinuous pad shaping surfaces of the tool simultaneously engage the polishing surface, and rotating the polishing pad while preventing translational movement of the tool relative to the pad so that the tool shapes the polishing surface of the pad to be more nearly flat.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: September 19, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Yi-yang Zhou, Eugene C. Davis
  • Patent number: 6112738
    Abstract: Methods of slicing ingots of semiconductor material into wafers using a wire saw. The wire saw includes a wire that is movable in a forward direction and a reverse direction for slicing the ingots. The methods include defining an identification region of each wafer to be sliced from the ingots and aligning an alignment feature of the ingots in approximately the same position relative to the wire saw for each of the ingots. The identification region of the wafer is adapted for marking with an identification mark after slicing. The methods also include slicing the ingot into wafers with the wire saw. The slicing step includes moving the wire in the forward and reverse directions during slicing except when slicing in the identification region of each wafer and moving the wire only in the forward direction when slicing in the identification region of each wafer. In slicing the ingot into wafers, thickness variations relative to the size of the identification mark are reduced in the identification region.
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: September 5, 2000
    Assignee: MEMC Electronics Materials, Inc.
    Inventors: Dale A. Witte, Tracy Ragan
  • Patent number: 6114245
    Abstract: A method of processing a semiconductor wafer comprises rough grinding the front and back surfaces of the wafer to quickly reduce the thickness of the wafer. The front and back surfaces are then lapped with a lapping slurry to further reduce the thickness of the wafer and reduce damage caused by the rough grinding. Lapping time is reduced by provision of the rough grinding step. The wafer is etched in a chemical etchant to further reduce the thickness of the wafer and the front surface of the wafer is polished using a polishing slurry to reduce the thickness of the wafer down to a predetermined final wafer thickness. A fine grinding step may be added to eliminate lapping and/or reduce polishing time.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: September 5, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Roland Vandamme, Yun-Biao Xin, Zhijian Pei
  • Patent number: 6100167
    Abstract: A process for removing copper from a boron doped, polished silicon wafer which contains copper on its polished surface and in its interior. In the process, the wafer is annealed at a temperature of at least about 75.degree. C. to increase the concentration of copper on the polished surface of the wafer and decrease the concentration of copper in the interior of the wafer. The polished surface of the annealed wafer is then cleaned to reduce the concentration of copper thereon. In addition, the annealing step is carried out at a temperature and a time such that the concentration of copper on the polished surface of the silicon will not increase by a factor of more than two upon storage of the annealed and cleaned wafer at room temperature for a period of 5 months.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: August 8, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Fabrizio Leoni, Marco Bricchetti, Alessandro Corradi
  • Patent number: 6093913
    Abstract: An electrical resistance heater for use in a crystal puller used for growing monocrystalline silicon ingots according to the Czochralski method comprises a heating element sized and shaped for disposition in the housing of the crystal puller around the crucible for applying heat to the crucible and silicon therein. The heating element includes heating segments connected together in an electric circuit. The segments have upper and lower sections and are arranged relative to each other so that when disposed around the crucible containing molten silicon the upper sections are disposed generally above a horizontal plane including the surface of the molten silicon and the lower sections are disposed generally below the horizontal plane. The upper sections are constructed to generate more heating power than the lower sections thereby to reduce a temperature gradient between the molten silicon at its surface and the ingot just above the surface of the molten silicon.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: July 25, 2000
    Assignee: MEMC Electronic Materials, Inc
    Inventors: Richard G. Schrenker, William L. Luter
  • Patent number: 6089285
    Abstract: A method of supplying source material in a crystal puller used to grow single crystal semiconductor material. Generally, the method includes receiving a bulk container of the source material at a facility having the crystal puller and configuring the bulk container for gravity feed of the source material from the container. The bulk container is transported to the crystal puller and a predetermined quantity of source material is dispensed directly from the bulk container into the crystal puller. Apparatus and a system for use in supplying source material are also disclosed.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: July 18, 2000
    Assignee: MEMC Electronics Materials, Inc.
    Inventors: Mark DeStefano, James Dean Eoff, Sr., Thomas H. Schulte, John M. Anderson, Eng Chin Yau, Donald R. Ruggeri, David W. Baldwin, Charles Lawrence Badino
  • Patent number: 6086678
    Abstract: A system for equalizing pressure across a gate adapted to selectively block a port connecting a wafer handling chamber to a process chamber of a reactor for depositing an epitaxial layer on a semiconductor wafer positioned in the process chamber. The system comprises a bypass passage connecting the process chamber to the wafer handling chamber for transporting gas between the process chamber and the wafer handling chamber when the gate is blocking the port connecting the wafer handling chamber to the process chamber of the reactor for equalizing pressure between the process chamber and the wafer handling chamber. The system also includes a bypass valve positioned along the bypass passage for selectively controlling gas flow through the bypass passage.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: July 11, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Gregory M. Wilson, Michael J. Ries, Thomas A. Torack
  • Patent number: 6057170
    Abstract: A method and system of measuring waviness of a silicon wafer. A memory stores data representative of the shape of the wafer at a plurality of positions on the wafer and a processor processes the data to determine a waviness parameter. The processor defines an inspection surface as a function of the data and calculates deviations between the inspection surface and a first reference plane at a plurality of positions on the inspection surface. The processor further defines a plurality of localized sites on the wafer and calculates deviations between the inspection surface and a second reference plane at a plurality of positions on the inspection surface for each site. The second reference plane is a function of the calculated deviations between the inspection surface for each site and the first reference plane. The processor then defines a waviness parameter for each site as a maximum variance of the calculated deviations between the inspection surface and the second reference plane.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: May 2, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Dale Andrew Witte
  • Patent number: 6053974
    Abstract: A heat shield for use in a crystal puller around a monocrystalline ingot grown out of a crucible in the crystal puller filled with molten semiconductor source material. The heat shield includes a reflector having a central opening sized and shaped for surrounding the ingot as the ingot is grown to reduce heat transfer from the crucible. The reflector is adapted to be supported in the crystal puller between the molten material and a camera aimed toward at three separate points on a meniscus formed between the ingot and an upper surface of the molten material. The reflector has at least three passages extending through the reflector. Each of the passages is located along an imaginary line extending between the camera and one of the points on the meniscus. This permits the camera to view the points so the positions of the points can be determined by the camera for calculating the diameter of the ingot while minimizing heat loss through the passages.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: April 25, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: William L. Luter, Lee W. Ferry
  • Patent number: 6039801
    Abstract: A continuous oxidation process and apparatus for using the same are disclosed. During growth of a semiconductor crystal an oxygen-containing gas is continuously injected into the crystal pulling apparatus in an exhaust tunnel downstream from the hot zone to continuously oxidize hypostoichiometric silicon dioxide, silicon vapor, and silicon monoxide produced in the hot zone during the crystal growth so as to minimize or eliminate the possibility of rapid over-pressurization of the apparatus upon exposure to the atmosphere.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: March 21, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: John D. Holder, Bayard K. Johnson
  • Patent number: 6039807
    Abstract: An epitaxial barrel reactor for depositing a material on a semiconductor wafer by a chemical vapor deposition process using a reactant gas. The barrel reactor includes a receptacle defining a reaction chamber sized to receive at least one semiconductor wafer. The receptacle has an inlet port for introducing reactant gas to the reaction chamber and an exhaust port for removing reactant gas from the reaction chamber. The reactor also includes an exhaust tube sealingly engageable with the exhaust port of the receptacle for transporting reactant gas to facility piping to remove the gas from the reaction chamber after the chemical vapor deposition process. In addition, the reactor includes an actuator spaced from the receptacle for moving the exhaust tube between an operating position in which the tube sealingly engages the exhaust port of the receptacle and a maintenance position in which the tube is spaced from the exhaust port to provide access to the receptacle.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: March 21, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Umberto Guarniero, Franco Magon, Enzo Bonanno
  • Patent number: 6030887
    Abstract: Process for the preparation of an epitaxial wafer having a total thickness variation and/or site total indicated reading of less than about 1.0 .mu.ms. The distance between the front and back surfaces of the epitaxial wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the epitaxial wafer in a stock removal step to reduce the thickness of the epitaxial wafer to the target thickness, T.sub.t, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and T.sub.t.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: February 29, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Ankur H. Desai, David L. Vadnais, Robert W. Standley
  • Patent number: 6026963
    Abstract: A moisture barrier bag for containing semiconductor wafers. The bag includes at least one opaque panel made of moisture barrier material, and at least one window panel made of at least partially transparent material. The window panel is joined in sealing relation to the opaque panel. The opaque panel and window panel are capable of defining a volume for receiving semiconductor wafers therein. The window panel permits optical inspection of semiconductor wafers received within the volume. The moisture barrier material has a moisture transmission rate which is sufficiently small to permit storage of semiconductor wafers within the volume for an extended period of time without damaging the wafers by moisture attack.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: February 22, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Aaron Leo Gray, III, Elizabeth C. Cooke
  • Patent number: 6019838
    Abstract: A crystal growing apparatus is able to provide dopant to a melt in the apparatus. A hopper is carrying dopant is integrated into a pull shaft of the apparatus so that dopant can be added to the melt without providing additional orifices in the apparatus or by opening the interior of the apparatus to the atmosphere.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: February 1, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Marcello Canella
  • Patent number: 6015335
    Abstract: Apparatus for dressing the cutting surfaces around a central opening of an annular inside diameter saw. The apparatus includes a base and a shaft mounted on the base for rotation on a longitudinal axis of the shaft. The shaft is adapted to be positioned adjacent the central opening of the saw. The apparatus also includes a fixture mounted on the shaft for holding a dressing stone in the central opening of the saw. In addition, the apparatus includes a motor for rotating the shaft to move the dressing stone held by the fixture along an arc centered on the longitudinal axis of the shaft into engagement with the cutting surfaces of the saw when the saw is rotating thereby to remove deposits from the cutting surfaces of the saw.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: January 18, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Russell Bradley Roberts
  • Patent number: 6006738
    Abstract: A method for cutting an ingot with a wire. The method includes the steps of moving a wire in a lengthwise direction and contacting an ingot with the moving wire. The method also includes the step of supplying an abrasive slurry containing cutting oil and abrasive particles having an average diameter of about 13 .mu.m to about 15 .mu.m to the ingot when the ingot and the wire are contacting. This results in the ingot being cut with the wire and abrasive particles.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: December 28, 1999
    Assignee: MEMC Japan, Ltd.
    Inventors: Kunio Itoh, Nobutaka Tanaka
  • Patent number: 6006736
    Abstract: A method and apparatus for washing a sliced silicon ingot reduces the consumption of detergent used to clean the ingot after it is sliced to define individual semiconductor wafers. The ingot is taken as a unit mounted to a holder after slicing to a pre-washing machine. The machine sprays jets of warm to hot water onto the ingot and holder to flush away dust generated during the slicing procedure which has adhered to the ingot. The water spray removes much of the dust. Thus when the ingot is subsequently washed with detergent, less dust must be removed thereby increasing the effective performance life of a given quantity of detergent.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: December 28, 1999
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Yoshihiro Suzuki, Koichi Kato, Keiichi Takami, Ryoichi Kawamura, Takehiro Watanabe, Masahiro Kosako
  • Patent number: 5994761
    Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, a central plane between the front and back surfaces, and a sink for crystal lattice vacancies at the front surface. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The wafer is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the crystal lattice vacancy sink to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: November 30, 1999
    Assignee: MEMC Electronic Materials SpA
    Inventors: Robert Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Patent number: 5990014
    Abstract: A low pressure in situ wafer cleaning process and apparatus are disclosed wherein a low pressure external combustion reactor 2 in combination with a low pressure furnace 14 produces a stream of a combustion product through the combustion of a halogenated hydrocarbon and oxygen. The combustion product is contacted with semiconductor wafers in the low pressure furnace to remove Group I and II metals. After a sufficient time has passed for cleaning, the combustion reactor and furnace are purged with an inert gas to remove the combustion product. In a preferred embodiment, the halogenated hydrocarbon is trans-1,2-dichloroethylene and the combustion product is vaporous hydrochloric acid.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: November 23, 1999
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Gregory M. Wilson, Charles R. Lottes
  • Patent number: 5980629
    Abstract: A method of reinforcing a crucible for the containment of molten semiconductor material in a Czochralski process, and of inhibiting formation of dislocations within a single crystal grown by the process. The crucible includes a body of vitreous silica having a bottom wall and a sidewall formation extending up from the bottom wall and defining a cavity for holding the molten semiconductor material. The sidewall formation and bottom wall each have an inner and an outer surface. A first devitrification promoter is deposited on the inner surface of the sidewall formation at a temperature below about 600.degree. C. The deposit is such that, when the crucible is heated above 600.degree. C., a first layer of substantially devitrified silica forms on the inner surface which is capable of promoting substantially uniform dissolution of the inner surface and reducing the release of crystalline silica particulates into the molten semiconductor material as a crystal is pulled from the molten semiconductor material.
    Type: Grant
    Filed: June 14, 1995
    Date of Patent: November 9, 1999
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Richard L. Hansen, Larry E. Drafall, Robert M. McCutchan, John D. Holder, Leon A. Allen, Robert D. Shelley