Patents Assigned to MEMC
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Patent number: 6315828Abstract: A continuous oxidation process and apparatus for using the same are disclosed. During growth of a semiconductor crystal an oxygen-containing gas is continuously injected into the crystal pulling apparatus in an exhaust tunnel downstream from the hot zone to continuously oxidize hypostoichiometric silicon dioxide, silicon vapor, and silicon monoxide produced in the hot zone during the crystal growth so as to minimize or eliminate the possibility of rapid over-pressurization of the apparatus upon exposure to the atmosphere.Type: GrantFiled: January 21, 2000Date of Patent: November 13, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: John D. Holder, Bayard K. Johnson
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Patent number: 6312517Abstract: A method of lowering the resistivity of resultant silicon crystal from a Czochralski crystal growing process by adding arsenic dopant to the melt in multiple stages.Type: GrantFiled: May 11, 2000Date of Patent: November 6, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Mohsen Banan, Milind Kulkarni, Charles Whitmer, II
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Patent number: 6312516Abstract: A process for growing a single crystal silicon ingot having an axially symmetric region substantially free of agglomerated intrinsic point defects. The ingot is grown generally in accordance with the Czochralski method; however, the manner by which the ingot is cooled from the temperature of solidification to a temperature which is in excess of about 900° C. is controlled to allow for the diffusion of intrinsic point defects, such that agglomerated defects do not form in this axially symmetric region. Accordingly, the ratio v/G0 is allowed to vary axially within this region, due to changes in v or G0, between a minimum and maximum value by at least 5%.Type: GrantFiled: June 25, 1999Date of Patent: November 6, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Vladimir Voronkov, Paolo Mutti
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Patent number: 6306733Abstract: A process for preparing an silicon epitaxial wafer. The wafer has a front surface having an epitaxial layer deposited thereon, a back surface, and a bulk region between the front and back surfaces, wherein the bulk region contains a concentration of oxygen precipitates. In the process, a wafer having interstitial oxygen atoms is first subjected to an oxygen precipitation heat treatment to cause the nucleation and growth of oxygen precipitates to a size sufficient to stabilize the oxygen precipitates. An epitaxial layer is then deposited on the surface of the oxygen precipitate stabilized wafer.Type: GrantFiled: July 27, 2000Date of Patent: October 23, 2001Assignee: MEMC Electronic Materials, SPAInventors: Robert Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
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Patent number: 6293139Abstract: A testing and analyzing method for determining the performance characteristics of a production lot of polishing pads. The first step requires polishing a plurality of semiconductor wafers with a selected number of polishing pads from the production lot of polishing pads. At least a portion of the surface area of each of the plurality of semiconductor wafers is divided into a plurality of sites. At least one wafer characteristic from each site is measured. The wafer characteristic from each site is incorporated into a discriminant function selected to predict the performance characteristics of a production lot of polishing pads by the quantitative level of the data obtained from a plurality of semiconductor wafers polished by the selected number of polishing pads.Type: GrantFiled: November 3, 1999Date of Patent: September 25, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Kevin A. Keller, Gerald A. Whitman, Jr.
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Patent number: 6287380Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process comprises controlling growth conditions, such as growth velocity, v, instantaneous axial temperature gradient, G0, and the cooling rate, within a range of temperatures at which silicon self-interstitials are mobile, in order to prevent the formation of these agglomerated defects. In ingot form, the axially symmetric region has a width, as measured from the circumferential edge of the ingot radially toward the central axis, which is at least about 30% the length of the radius of the ingot. The axially symmetric region additionally has a length, as measured along the central axis, which is at least about 20% the length of the constant diameter portion of the ingot.Type: GrantFiled: April 9, 1998Date of Patent: September 11, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Joseph C. Holzer
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Patent number: 6287382Abstract: An electrode assembly for use with an electrical resistance heater mounted in a housing of a crystal puller used for growing monocrystalline silicon ingots according to the Czochralski method comprises an electrode having a first end in electrical connection with the heater within the housing and an outer end. The electrode extends through the crystal puller housing such that the outer end of the electrode is generally external of the housing. The portion of the electrode within the housing is generally solid in cross-section along the entire length of said portion and free of any internal cooling passages. An electrical conductor is electrically connected to a portion of the electrode extending externally of the housing for supplying electrical current to the electrode from a source of electrical current for conduction inward along the electrode to the heater located in the housing.Type: GrantFiled: October 13, 1998Date of Patent: September 11, 2001Assignee: MEMC Electronic Materials, Inc.Inventor: Carl F. Cherko
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Patent number: 6284039Abstract: The present invention is directed to a set of epitaxial silicon wafers assembled in a wafer cassette, boat or other wafer carrier. Each wafer comprises a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.Type: GrantFiled: October 13, 1999Date of Patent: September 4, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Luciano Mule'Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
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Patent number: 6284040Abstract: An improved process for forming a single crystal silicon ingot from solid, varying sized chunks of polycrystalline silicon source material according to the Czochralski method. The process includes classifying each chunk of source material by size, placing chunks of source material into a crucible to form a stack in the crucible. The chunks are generally placed within at least three regions of the crucible that are pre-selected according to the size classifications of the chunks. The stack within the crucible is melted in an inert environment at an elevated temperature to form a source melt, and the temperature of the crucible and the source melt is stabilized to an equilibrium level suitable for crystal growth. The single crystal silicon ingot is pulled from the source melt according to the Czochralski method. In another aspect, the step of melting the stack is taken while the crucible has an ambient pressure that is greater than an ambient pressure when the step of stabilizing the temperature is taken.Type: GrantFiled: January 13, 1999Date of Patent: September 4, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: John D. Holder, Hariprasad Sreedharamurthy
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Patent number: 6285011Abstract: An electrical resistance heater for use in a crystal puller used for growing monocrystalline ingots according to the Czochralski method comprises a heating element sized and shaped for placement in the housing of the crystal puller for radiating heat within the housing. The heating element has heating segments arranged in a generally side-by-side relationship and electrically connected together. Each heating segment comprises a web and a flange projecting outwardly from the web in non-coplanar relationship therewith. This reduces the cross-sectional area of the heating segment for increasing the electrical resistance and power output of the heater while providing desired structural rigidity.Type: GrantFiled: October 12, 1999Date of Patent: September 4, 2001Assignee: MEMC Electronic Materials, Inc.Inventor: Carl F. Cherko
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Patent number: 6284384Abstract: This invention is directed to a novel a single crystal silicon wafer. The wafer comprises: (a) two major generally parallel surfaces (ie., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer.Type: GrantFiled: February 16, 1999Date of Patent: September 4, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Gregory M. Wilson, Jon A. Rossi, Charles C. Yang
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Patent number: 6257954Abstract: An apparatus and process for chemical-mechanical polishing an edge of a semiconductor wafer using a heated polishing pad and a heated liquid chemical slurry. The apparatus includes a rotatable drum having a cylindric outer surface, a heatable mat positioned around the outer surface of the drum, and a polishing pad in generally parallel arrangement with the mat. A wafer holder, a container of liquid slurry, and a slurry delivery system are also included. The process includes the steps of heating a liquid slurry to an elevated temperature and applying heat to the polishing pad from an underside of the polishing pad to elevate the temperature of the polishing pad. A peripheral edge of a semiconductor wafer is engaged against a polishing side of the polishing pad, and a relative motion is effected between the wafer and the pad while simultaneously dispensing the heated slurry onto a region where the edge of the wafer engages the pad.Type: GrantFiled: February 23, 2000Date of Patent: July 10, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Kan-Yin Ng, Robert J. Walsh, Henry Erk, Dennis Buese
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Patent number: 6254672Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C., and (iii) a cooling rate of the crystal from a solidification temperature to about 1,050° C., in order to cause the formation of an axially symmetrical segment which is substantially free of agglomerated intrinsic point defects.Type: GrantFiled: April 9, 1998Date of Patent: July 3, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Robert A. Falster, Joseph C. Holzer, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
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Patent number: 6241818Abstract: A method and system for controlling growth of a taper portion of a semiconductor single crystal based on the slope of the taper. A crystal drive unit pulls the growing crystal from a melt at a target pull rate that substantially follows an initial velocity profile for growing the taper. A controller calculates a taper slope measurement as a function of a change in crystal diameter relative to a change in crystal length. The controller then generates an error signal as a function of the difference between the taper slope measurement and a target taper slope and provides a pull rate correction to the crystal drive unit as a function of the error signal. In turn, the crystal drive unit adjusts the pull rate according to the pull rate correction to reduce the difference between the taper slope measurement and the target taper slope. The target taper slope is defined by a function having a generally exponential component and a generally linear component.Type: GrantFiled: April 7, 1999Date of Patent: June 5, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Steven L. Kimbel, Robert R. Wyand, III
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Patent number: 6238483Abstract: A device for supporting a semiconductor ingot during growth of the ingot. The device includes a chuck in which is mounted a seed. The seed includes an elongate rod having one end projecting from the chuck for growth of the ingot thereon. A latch pin secures the seed in the chuck in a removable manner. The chuck is suspended in a semiconductor furnace. The chuck, seed and latch pin and interengaged in a manner to reduce forming flaws in the ingot.Type: GrantFiled: August 31, 1999Date of Patent: May 29, 2001Assignee: MEMC Electronic Materials, Inc.Inventor: Carl F. Cherko
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Patent number: 6236104Abstract: The present invention relates to a silicon on insulator (“SOI”) structure having a low defect density device layer and, optionally, a handle wafer having improved gettering capabilities. The device layer comprises a central axis, a circumferential edge, a radius extending from the central axis to the circumferential edge, and a first axially symmetric region which is substantially free of agglomerated intrinsic point defects. Additionally, the present invention is directed to such a SOI structure which has a Czochralski single crystal silicon handle wafer which is capable of forming an ideal, non-uniform depth distribution of oxygen precipitates upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process.Type: GrantFiled: August 31, 1999Date of Patent: May 22, 2001Assignee: MEMC Electronic Materials, Inc.Inventor: Robert J. Falster
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Patent number: 6231628Abstract: A method of separating, recovering and reusing components of an exhausted slurry used in slicing silicon wafers from a silicon ingot. In the method, the viscosity of the exhausted slurry is reduced and the lubricating fluid component of the slurry is separated from solids and collected, the collected lubricating fluid component being suitable for reuse in the preparation of a fresh slurry without any additional separation steps being necessary. Additionally, the separated solids may be collected and further separated into an unspent abrasive grain component, which is suitable for reused in the preparation of a fresh slurry, and a waste product containing silicon particulate and spent abrasive grains.Type: GrantFiled: July 1, 1999Date of Patent: May 15, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Carlo Zavattari, Guido Fragiacomo
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Patent number: 6230720Abstract: A process for cleaning a final polished semiconductor wafer in a single operation (i.e., following final polishing, a process or action is directed at the wafer which includes drying the wafer only once, thereby yielding a polished wafer surface substantially free of contaminants). The process comprising contacting the polished wafer with an aqueous solution comprising an oxidizing agent to oxidize organic carbon on the surface of the polished wafer. After oxidizing the organic carbon, immersing the polished wafer in an megasonically agitated alkaline cleaning solution to reduce the surface concentration of contaminant particles exceeding 0.2 &mgr;m in diameter. Withdrawing the polished wafer from the alkaline cleaning solution and rinsing it with deionized water. After rinsing, immersing the polished wafer in an acidic cleaning solution to reduce the surface concentration of contaminant metal atoms. Withdrawing the polished wafer from the acidic cleaning solution and immersing it in an ozonated aqueous bath.Type: GrantFiled: June 29, 2000Date of Patent: May 15, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: M. Rao Yalamanchili, Kari B. Myli, Larry W. Shive
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Patent number: 6227944Abstract: A method for processing a semiconductor wafer sliced from a single-crystal ingot comprises subjecting the front and back surfaces of the wafer to a lapping operation to reduce the thickness of the wafer and to remove damage caused during slicing of the wafer. The wafer is then subjected to an etching operation to further reduce the thickness of the wafer and to further remove damage remaining after the lapping operation. The wafer is subsequently subjected to a double-side polishing operation to uniformly remove damage from the front and back surfaces caused by the lapping and etching operations, thereby improving the flatness of the wafer and leaving polished front and back surfaces. Finally, the back surface of the wafer is subjected to a back surface damaging operation in which damage is induced in the back surface of the wafer while the front surface is substantially protected against being damaged or roughened.Type: GrantFiled: March 25, 1999Date of Patent: May 8, 2001Assignee: MEMC Electronics Materials, Inc.Inventors: Yun-Biao Xin, Ichiro Yoshimura, Henry F. Erk, Ralph V. Vogelgesang, Stephen Wayne Hensiek
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Patent number: 6214109Abstract: A process and apparatus for regulating the concentration and distribution of oxygen in a single crystal silicon rod pulled from a silicon melt, optionally doped with antimony or arsenic, in accordance with the Czochralski method wherein an atmosphere is maintained over the melt. In batch embodiments of the process, the gas pressure of the atmosphere over the melt is progressively increased to a value in excess of 100 torr as the fraction of silicon melt solidified increases. In continuous embodiments of the process, the gas pressure of the atmosphere over the melt is maintained at or near a constant value in excess of 100 torr. The process and apparatus are further characterized in that a controlled flow of inert gas is used to remove vapors and particulate away from the surface of the rod and melt, resulting in the production of a single crystal silicon rod having zero dislocations.Type: GrantFiled: March 16, 1999Date of Patent: April 10, 2001Assignee: MEMC Electronic Materials, Inc.Inventor: John D. Holder