Patents Assigned to MEMC
  • Patent number: 6454635
    Abstract: A method for repairing a wafer carrier after plural processing operations during which the carrier holds a plurality of semiconductor wafers in a processing apparatus which removes wafer material by at least one of abrading and chemical reaction. The wafer carrier has holes for receiving respective ones of the wafers and removable annular inserts for each hole. Each insert is receivable in a respective one of the holes for engaging a peripheral edge of one of the wafers. The thickness of the insert is reduced during the successive processing operations. The method includes removing at least one of the inserts from the wafer carrier and installing at least one new insert in the wafer carrier having a thickness substantially greater than a minimum thickness to extend the useful life of the wafer carrier and to improve the flatness and parallelism of surfaces of wafers processed using the wafer carrier.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: September 24, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Guoqiang David Zhang, Yun-Biao Xin, Henry F. Erk
  • Publication number: 20020127766
    Abstract: A process for manufacturing a semiconductor wafer comprises first etching the wafer to reduce damage on the front and back surfaces. An epitaxial layer is grown on the etched front surface of the semiconductor wafer to improve the surface roughness of the front surface. Finally, the front surface of the wafer is final polished to further improve the surface roughness of the front surface.
    Type: Application
    Filed: December 21, 2001
    Publication date: September 12, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Michael J. Ries, Gregory M. Wilson, Robert W. Standley, Larry W. Shive, Jon A. Rossi
  • Patent number: 6447601
    Abstract: A crystal puller for growing monocrystalline silicon ingots according to the Czochralski method includes a housing and a crucible in the housing for containing molten silicon. The crucible has a side wall having a transmittance of at least about 80% generally throughout a light wavelength range of about 500 to about 2500 nanometers. A pulling mechanism is included for pulling a growing ingot upward from the molten silicon. In operation, polycrystalline silicon is charged to the crucible and the crucible is heated to melt the polycrystalline silicon for forming a molten silicon melt in the crucible. A seed crystal is then brought into contact with the molten silicon in the crucible and a monocrystalline silicon ingot is pulled up from the molten silicon.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: September 10, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Richard Joseph Phillips, Larry E. Drafall, Kirk D. McCallum
  • Publication number: 20020121238
    Abstract: A single crystal silicon wafer comprising a front surface, a back surface, a lateral surface joining the front and back surfaces, a central axis perpendicular to the front and back surfaces, and a segment which is axially symmetric about the central axis extending substantially from the front surface to the back surface in which crystal lattice vacancies are the predominant intrinsic point defect, the segment having a radial width of at least about 25% of the radius and containing agglomerated vacancy defects and a residual concentration of crystal lattice vacancies wherein (i) the agglomerated vacancy defects have a radius of less than about 70 nm and (ii) the residual concentration of crystal lattice vacancy intrinsic point defects is less than the threshold concentration at which uncontrolled oxygen precipitation occurs upon subjecting the wafer to an oxygen precipitation heat treatment.
    Type: Application
    Filed: January 2, 2002
    Publication date: September 5, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Paolo Mutti, Fancesco Bonoli
  • Patent number: 6444027
    Abstract: A modified susceptor for use in an epitaxial deposition apparatus and process is disclosed. The modified susceptor has an inner annular ledge capable of supporting a semiconductor wafer and has a plurality of holes in the surface to allow cleaning gas utilized during an epitaxial deposition process to pass through the susceptor and contact substantially the entire back surface of the semiconductor wafer and remove a native oxide layer. Also, the plurality of holes on the susceptor allows dopant atoms out-diffused from the back surface during the epitaxial deposition process to be carried away from the front surface in an inert gas stream and into the exhaust such that autodoping of the front surface is minimized.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: September 3, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Charles Chiun-Chieh Yang, Robert W. Standley
  • Publication number: 20020113265
    Abstract: The present invention relates to a silicon on insulator (“SOI”) structure having a low defect density device layer and, optionally, a handle wafer having improved gettering capabilities. The device layer comprises a central axis, a circumferential edge, a radius extending from the central axis to the circumferential edge, and a first axially symmetric region which is substantially free of agglomerated intrinsic point defects. Additionally, the present invention is directed to such a SOI structure which has a Czochralski single crystal silicon handle wafer which is capable of forming an ideal, non-uniform depth distribution of oxygen precipitates upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process.
    Type: Application
    Filed: January 3, 2002
    Publication date: August 22, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventor: Robert J. Falster
  • Publication number: 20020112658
    Abstract: This invention relates to a process for monitoring the gaseous environment within a sealed crystal pulling furnace, used for the growth of an ingot of a semiconductor material in a growth chamber maintained at a sub-atmospheric pressure. The process comprises sealing the chamber, reducing the pressure within the sealed chamber to a sub-atmospheric level, introducing a process gas into the chamber to purge the chamber and form a gaseous environment therein, and analyzing the gaseous environment within the chamber for the presence of a contaminant gas in a concentration which is greater than the concentration of the contaminant gas in the process gas.
    Type: Application
    Filed: December 3, 2001
    Publication date: August 22, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: John D. Holder, Shawn K. McGuire, Matthew J. Burger
  • Patent number: 6435474
    Abstract: A non-contaminating gas-tight valve for controlling a flow of granular polysilicon. The valve has a spherical valve member formed from single-crystal polysilicon, so that any particles worn from the valve member during use will be non-contaminating polysilicon. The valve member has a passage through which granular polysilicon flows when the valve is in an open position. When rotated perpendicular to the flow, the passage no longer permits movement of granular polysilicon through the valve. The valve member has a smooth finish and is wiped clean when rotated against non-abrasive upper and lower seats, reducing the likelihood of valve member wear. A cavity between the valve member and the valve body allows for removal of excess granular polysilicon from the valve, inhibiting the valve from seizing due to excess granular polysilicon slipping past the upper valve seat and accumulating within the valve. The valve additionally forms a gas-tight seal between an upstream and downstream side of the valve.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: August 20, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Dick Stetson Williams, Treaf Andrus, Timothy J. Kulage, Ken Harrell
  • Patent number: 6432197
    Abstract: The present invention relates to a process for the treatment of Czochralski single crystal silicon wafers to dissolve existing oxygen clusters and precipitates, while preventing their formation upon a subsequent oxygen precipitation heat treatment. The process comprises rapid thermal annealing the wafer to dissolve existing oxygen clusters and precipitates. The rapid thermal anneal is performed in an atmosphere capable of oxidizing the surface of the wafer thereby causing an inward flux of silicon self-interstitial atoms in order to reduce the number density of vacancies in the single crystal silicon to a value such that oxygen precipitates will not form if the wafer is subsequently subjected to an oxygen precipitation heat-treatment.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: August 13, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Robert J. Falster
  • Publication number: 20020100410
    Abstract: The present invention relates to a process for preparing a single crystal silicon ingot, as well as to the ingot or wafer resulting therefrom. The process comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, and (iii) a cooling rate of the crystal from solidification to about 750° C., in order to cause the formation of a segment having a first axially symmetric region extending radially inward from the lateral surface of the ingot wherein silicon self-interstitials are the predominant intrinsic point defect, and a second axially symmetric region extending radially inward from the first and toward the central axis of the ingot.
    Type: Application
    Filed: January 22, 2002
    Publication date: August 1, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Chang Bum Kim, Steven L. Kimbel, Jeffrey L. Libbert, Mohsen Banan
  • Publication number: 20020092460
    Abstract: A process for growing single crystal silicon ingots which are substantially free of agglomerated intrinsic point defects. An ingot is grown generally in accordance with the Czochralski method. No portion of the ingot cools to a temperature which is less than a temperature TA at which agglomeration of intrinsic point defects in the ingot occurs during the time the ingot is being grown. The achievement of defect free ingots is thus substantially decoupled from process parameters, such as pull rate, and system parameters, such as axial temperature gradient in the ingot.
    Type: Application
    Filed: October 23, 2001
    Publication date: July 18, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Harold W. Korb
  • Publication number: 20020088389
    Abstract: A method and apparatus for the high throughput epitaxial growth of a layer on the surface of a substrate by chemical vapor deposition is provided. In one embodiment, the method of the present invention comprises placing the substrate within a reactor vessel and passing a horizontal flow of reactant gas comprising a precursor chemical through the reactor vessel. The flow of the reactant gas is defined as having a Reynolds number of at least about 5000. The substrate is heated to a temperature sufficient to thermally decompose the precursor chemical and deposit an epitaxial layer on the substrate. In accordance with a preferred embodiment of the present invention, the substrate is placed within the reactor vessel at a position such that the flow of the reactant gas is characterized as a fully developed turbulent flow.
    Type: Application
    Filed: November 15, 2001
    Publication date: July 11, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Srikanth Kommu, Gregory M. Wilson
  • Patent number: 6416836
    Abstract: A single crystal silicon wafer having a central axis, a front side and a back side which are generally perpendicular to the central axis, a central plane between the front and back sides, a circumferential edge, and a radius extending from the central axis to the circumferential edge. The wafer comprises first and second axially symmetric regions. The first axially symmetric region extends radially inwardly from the circumferential edge, contains silicon self-interstitials as the predominant intrinsic point defect, and is substantially free of agglomerated interstitial defects. The second axially symmetric region has vacancies as the predominant intrinsic point defect, comprises a surface layer extending from the front side toward the central plane and a bulk layer extending from the surface layer to the central plane, wherein the number density of agglomerated vacancy defects present in the surface layer is less than the concentration in the bulk layer.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: July 9, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Martin Jeffrey Binns, Alan Wang
  • Publication number: 20020083887
    Abstract: A process for controlling the amount of insoluble gas trapped by a silicon melt is disclosed. Polycrystalline silicon is charged to a crucible in a crystal pulling apparatus and the apparatus sealed and evacuated. After evacuation, the crystal pulling apparatus is backfilled at least once with a gas having a high solubility in silicon, such as nitrogen. The highly soluble gas fills in cavities between the polycrystalline silicon pieces and between the pieces and the crucible such that when the silicon is melted and bubbles form in the molten silicon the bubbles will solubilize into the melt instead of becoming entrapped in the growing crystal.
    Type: Application
    Filed: October 23, 2001
    Publication date: July 4, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventor: John D. Holder
  • Publication number: 20020083889
    Abstract: A single crystal silicon wafer having a central axis, a front side and a back side which are generally perpendicular to the central axis, a central plane between the front and back sides, a circumferential edge, and a radius extending from the central axis to the circumferential edge. The wafer comprises first and second axially symmetric regions. The first axially symmetric region extends radially inwardly from the circumferential edge, contains silicon self-interstitials as the predominant intrinsic point defect, and is substantially free of agglomerated interstitial defects. The second axially symmetric region has vacancies as the predominant intrinsic point defect, comprises a surface layer extending from the front side toward the central plane and a bulk layer extending from the surface layer to the central plane, wherein the number density of agglomerated vacancy defects present in the surface layer is less than the concentration in the bulk layer.
    Type: Application
    Filed: February 11, 2002
    Publication date: July 4, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Martin Jeffrey Binns, Alan Wang
  • Publication number: 20020086539
    Abstract: The present invention is directed to a process for reclaiming for reuse a single crystal silicon wafer removed from an aborted semiconductor device fabrication process. The process includes (a) subjecting the wafer to an oxide growth step to form an oxide layer having a thickness greater than 2 nanometers, (b) thinning the wafer by removing material from substantially the entire front surface to provide a thinned wafer having a thinned precipitate free zone, and (c) polishing the front surface of the thinned wafer to a specular finish.
    Type: Application
    Filed: December 13, 2001
    Publication date: July 4, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventor: Robert J. Falster
  • Publication number: 20020078880
    Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region in which vacancies are the predominant intrinsic point defect and which is substantially free of agglomerated vacancy intrinsic point defects, wherein the first axially symmetric region has a width which is at least about 50% of the length of the radius of the ingot, and a process for the preparation thereof.
    Type: Application
    Filed: October 24, 2001
    Publication date: June 27, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Joseph C. Holzer, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
  • Publication number: 20020078882
    Abstract: An apparatus and method are provided for forming a denuded zone and an epitaxial layer on a semiconductor wafer used in manufacturing electronic components. The denuded zone and epitaxial layer are formed in one chamber. The apparatus includes a plurality of upstanding pins immovably mounted on a susceptor and maintain a semiconductor wafer spaced from the susceptor during both application of the epitaxial layer and formation of the denuded zone. Fast cooling of the wafer is accomplished by having the wafer out of conductive heat transfer relation with the susceptor during cooling thereof.
    Type: Application
    Filed: January 15, 2002
    Publication date: June 27, 2002
    Applicant: MEMC Electronic Materials Inc.
    Inventors: Tom Torack, Michael J. Ries
  • Patent number: 6409826
    Abstract: The present invention relates a process for the preparation of single crystal silicon, which contains an axially symmetric region which is free of agglomerated intrinsic point defects. The process for growing the single crystal silicon including controlling the ratio v/G0, where v is the growth velocity and G0 is the average axial temperature gradient during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C., and a cooling rate of the crystal from a solidification temperature to about 1,050° C., in order to cause the formation of an axially symmetrical segment which is substantially free of agglomerated intrinsic point defects. The control of V/G0 accomplished by controlling heat transfer at the melt/solid interface.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: June 25, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert A. Falster, Joseph C. Holzer, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
  • Patent number: 6409827
    Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process including controlling growth conditions, such as growth velocity, v, instantaneous axial temperature gradient, G0, and the cooling rate, within a range of temperatures at which silicon self-interstitials are mobile, in order to prevent the formation of these agglomerated defects. The control of G0 is accomplished by controlling heat transfer at the melt/solid interface.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: June 25, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Joseph C. Holzer