Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: In a manufacturing method of a semiconductor device according to one embodiment, a first gas containing a first metal element is introduced into a chamber having a substrate housed therein. Next, the first gas is discharged from the chamber using a purge gas. Subsequently, a second gas reducing the first gas is introduced into the chamber. Next, the second gas is discharged from the chamber using the purge gas. Further, a third gas different from the first gas, the second gas, and the purge gas is introduced into the chamber at least either at a time of discharging the first gas or at a time of discharging the second gas.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.

Abstract: A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

Abstract: A memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory. The controller includes a processor, a storage circuit including a plurality of rewritable storage circuits that store timing data of a first timing information group which is settable by the processor, and a power source control circuit configured to trigger parallel execution of a plurality of power source control functions according to the timing data of the first timing information group read from the storage circuit.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.

Abstract: According to one embodiment, a template includes a base body, and a first film. The base body has a first surface and a second surface. The first surface includes silicon oxide and spreads along a first plane. The second surface crosses the first plane. The first film includes aluminum oxide. A direction from the second surface toward the first film is aligned with a direction perpendicular to the second surface. A thickness of the first film along the direction perpendicular to the second surface is not less than 0.3 nm and not more than 10 ?m. The first surface includes an unevenness.

Abstract: A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

Abstract: According to one embodiment, a data storage apparatus includes a controller with a data protection function. The controller manages first and second personal identification data. The first personal identification data only includes authority to request inactivation of the data protection function. The second personal identification data includes authority to request inactivation of the data protection function and activation of the data protection function. The controller permits setting of the first personal identification data, when the second personal identification data is used for successful authentication and the first personal identification data is an initial value, or when the data protection function is in an inactive state.

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A plasma treatment apparatus includes a discharge device generating plasma under atmospheric pressure, and a nonmetallic tube capable of advancing the plasma generated in the discharge device. The discharge device includes a discharge body with an internal space, and the plasma being generated in the internal space. The nonmetallic tube is connected to the discharge body, and includes a material different from a material of the discharge body. The plasma is released from the nonmetallic tube to an environment under atmospheric pressure.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, first and second pillars, and a first member. The first conductive layer includes a first portion, a second portion, and a third portion above the second portion. The second conductive layers are stacked above the first conductive layer. The first pillar includes a first semiconductor layer in contact with the first portion in a direction crossing the stacked direction. The second pillar is provided to penetrate the second conductive layers and the third portion in the stacked direction. The first member is provided between the first and second pillars and between the second and third portions.

Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

Abstract: An optical characteristics measuring device includes a first light source capable of irradiating a sample with light and a second light source capable of irradiating the sample with microwaves. A measuring device measures microwave power of the reflection of the microwaves from the sample. A calculation unit calculates a parameter relating to the electrical conductivity of the sample using the microwave power of the reflected waves measured by the measuring device. A control unit controls the intensity of the light of the first light source so that the parameter becomes approximately a predetermined value. The calculation unit specifies first to n-th intensities of the light at which the parameter becomes approximately the predetermined value for each of the first to n-th wavelengths of the light and obtains relationships between the first to n-th wavelengths and the first to n-th intensities corresponding to the respective first to n-th wavelengths.

Abstract: According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode.