Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A gas supply member according to an embodiment includes: a base material that has a gas flow path capable of flowing a gas from an upstream side to a downstream side, a main surface arranged on the downstream side of the gas flow path in a direction intersecting an extending direction of the gas flow path, and a discharge port connecting the gas flow path and the main surface; and a film that contains at least one of yttria, yttrium oxyfluoride, yttrium fluoride, alumina, and aluminum nitride and covers the main surface and a surface of the discharge port of the base material. The film covers the main surface and the surface of the discharge port such that a surface of the film does not have a surface orientation portion of which a normal intersects a normal of the main surface at 45° to 75°.

Abstract: According to one embodiment, an arithmetic processor generates unknown code distribution information, for an unknown test code to which no failure mode has been specified, and determines whether labeling of the unknown code distribution information is performable. The arithmetic processor determines whether the unknown code distribution information agrees to known code distribution information, when labeling of the unknown code distribution information is performable. The arithmetic processor determines whether the unknown code satisfies a classification minimum requirement of the agreed known code. The arithmetic processor presents a content of EFA measurement that assumes a failure mode corresponding to the known code, when the unknown code distribution information agrees to the known code distribution information, and the unknown code satisfies the classification minimum requirement of the known code.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer, a first electrode, first to third layers, and nitride portions of nitride molecules. The first layer is provided between the semiconductor layer and the first electrode. The second layer is provided between the first layer and the first electrode. The second energy of a conduction band edge of the second layer is lower than a first energy of a conduction band edge of the first layer. The second layer includes a first region and a second region. The first region is provided between the first layer and the second region. The third layer is provided between the second layer and the first electrode. The third energy of a conduction band edge of the third layer is higher than the second energy.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array; a first insulating layer; and a passivation film. The memory cell array includes first interconnect layers and a first memory pillar. The first interconnect layers extend in a first direction substantially parallel to a semiconductor substrate. The first memory pillar passes through the first interconnect layers and extends in a second direction substantially perpendicular to the semiconductor substrate. The first insulating layer is provided above the memory cell array. The passivation film is provided on the first insulating layer, and includes a protrusion at least above the memory cell array and between the passivation film and the first insulating layer.

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

Abstract: According to one embodiment, a controller is configured to calculate a matching rate of grid shapes between each semiconductor wafer of a first semiconductor wafer group and each semiconductor wafer of a second semiconductor wafer group, and generate pairing information, into which combinations of semiconductor wafers used in calculation of matching rates are registered when the matching rates fall within a predetermined range. Further, the controller is configured to select a first semiconductor wafer to be held by a first semiconductor wafer holder from the first semiconductor wafer group, and select a second semiconductor wafer from semiconductor wafers of the second semiconductor wafer group, which are paired with the first semiconductor wafer, with reference to the pairing information.

Abstract: According to an embodiment, an information processing apparatus includes a non-volatile memory manager. The non-volatile memory manager is configured to save, in a non-volatile memory section, information of a plurality of storage sections to be read after rebooting. The non-volatile memory section is configured to keep storing information even if power is off.

Abstract: According to the embodiments, a template in which a main pattern is placed on a pattern-formed surface of a template substrate, the main pattern being formed by a concave and convex pattern, the template substrate being transparent to an electromagnetic wave with a predetermined wavelength is provided. The template includes a first mark in which line-shaped first concave patterns and first convex patterns are alternately placed in a width direction on the pattern-formed surface. The first convex pattern includes a first light-blocking portion and a first translucent portion. The first light-blocking portion is a region including a first side surface in the width direction and being covered with a metal film. The first translucent portion is a region including a second side surface in the width direction and being not covered with the metal film.

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A system and method for controlling a SSD in response to a power failure event of a main power supply to the SSD. The method includes receiving and storing write commands and associated data payloads for execution on the SSD in volatile memory, detecting the power failure event on the SSD, supplying backup power to the SSD during the power failure event, and executing one or more write commands stored in the volatile memory by storing the associated data payloads in a non-volatile memory on the SSD using the backup power. In response to the execution, removing the one or more write commands from the cache such that one or more unexecuted write commands and the associated data payloads remain in the cache, and storing a list of the one or more unexecuted write commands, but not the associated data payloads, in non-volatile memory using the backup power.

Abstract: A plasma processing apparatus of an embodiment includes a chamber, an introducing part, a substrate electrode, a high-frequency power source, a low-frequency power source, and a switching mechanism. The introducing part introduces a process gas into the chamber. The substrate electrode is disposed in the chamber, a substrate is directly or indirectly mounted on the substrate electrode, and the substrate electrode includes a first and a second electrode elements alternately arranged. The high-frequency power source outputs a high-frequency voltage of 40 MHz or more for ionizing the process gas to generate plasma. The low-frequency power source outputs a low-frequency voltage of 20 MHz or less for introducing ions from the plasma. The switching mechanism applies the low-frequency voltage alternately to the first and the second electrode elements.

Abstract: A method performed by a controller of a solid state drive (SSD) comprising receiving from a host a write request to store write data in a nonvolatile semiconductor storage device of the SSD. The method also comprises identifying a first codeword and a second codeword stored in the nonvolatile storage device, the first codeword and the second codeword configured to store write data corresponding to the write request. Responsive to the write request, the method comprises writing a first portion of the write data to the first codeword and writing a second portion of the write data to the second codeword, and sending a message to the host once the write data has been written to the nonvolatile semiconductor storage device. The first and second codewords are adjacently stored, and the write data has a length that is greater than the length of the first and second codewords.

Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.

Abstract: According to one embodiment, a processing device includes: a first circuit configured to execute first processing using a first matrix to first data of a size of 5×5 within input data to generate second data; a second circuit configured to execute second processing using a second matrix to third data of a size of 3×3 to generate fourth data; a third circuit configured to execute a product-sum operation on the second data and the fourth data; and a fourth circuit configured to execute third processing using a third matrix on a result of the product-sum operation on the second data and the fourth data to obtain a first value corresponding to a result of a product-sum operation on the first data and the third data.

Abstract: A semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact plug CP1 which extends in the second area in the first direction and is connected to the logic circuit.

Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Abstract: A resource management system in a data center one or more data storage resource providers and a transaction server. The transaction server is configured to receive, from a client, a request for read and/or write access for a data storage resource, the request comprising one or more specifications, to provide, to the one or more data storage resource providers, at least a portion of the request, and to receive, from the one or more data storage resource providers, respective responses to the request, the responses respectively comprising one or more allocation options. The transaction server is further configured to select one of the one or more allocation options for registration, and register the selected allocation option with a data manager. At least one of the one or more data storage providers is configured to provide the data storage resource in accordance with the registered allocation option.