Patents Assigned to Memory Corporation
  • Patent number: 11114322
    Abstract: According to one embodiment, a mold includes a substrate clamping surface, a cavity, a suction part, a vent, an intermediate cavity, and an opening/closing part. The substrate clamping surface contacts a surface of a processing substrate. The cavity is recessed from the substrate clamping surface. The suction part is recessed from the substrate clamping surface. The vent is provided on a path between the cavity and the suction part, communicates with the cavity, is recessed from the substrate clamping surface to a vent depth. The intermediate cavity is provided between the vent and the suction part on the path, communicates with the vent, and is recessed from the substrate clamping surface to an intermediate cavity depth deeper than the vent depth. The opening/closing part opens and closes the path and is provided between the intermediate cavity and the suction part on the path.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 7, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takeori Maeda, Ryoji Matsushima, Makoto Kawaguchi, Masaaki Wakui
  • Publication number: 20210271781
    Abstract: In one embodiment, a guide layout creating apparatus includes a selection module that selects a first point as a point on which a guide to array a plurality of particles in a first array is arranged. The apparatus further includes a calculation module that calculates first free energy when the plurality of particles are arrayed in the first array by the guide arranged on the first point, and second free energy when the plurality of particles are arrayed in a second array by the guide arranged on the first point, a type of the second array being different from a type of the first array. The apparatus further includes a determination module that determines whether the first point is employed as the point on which the guide is arranged on the basis of the first free energy and the second free energy.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Applicant: Toshiba Memory Corporation
    Inventor: Hironobu SATO
  • Patent number: 11107802
    Abstract: In one embodiment, a semiconductor device includes a first substrate, and a plurality of electrode layers provided above the first substrate and stacked in a first direction. The device further includes a first semiconductor layer extending in the first direction in the plurality of electrode layers, and a metal layer provided above an uppermost one of the plurality of electrode layers and extending to cross the first direction. The device further includes a second semiconductor layer including an impurity diffusion layer that is provided between the first semiconductor layer and the metal layer, electrically connects the first semiconductor layer with the metal layer, and has an impurity concentration higher than an impurity concentration of the first semiconductor layer.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 31, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Nakaki
  • Publication number: 20210265181
    Abstract: According to embodiments, a substrate treatment apparatus includes a housing, a heater and a pipe. The housing stores solution containing phosphoric acid and houses a substrate including a silicon substrate. The heater heats the solution over a normal boiling point of the solution. The pipe supplies heated solution heated by the heater into the housing while generating air bubbles.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshinori KITAMURA, Katsuhiro SATO, Hiroaki ASHIDATE
  • Patent number: 11101325
    Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 24, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
  • Patent number: 11101285
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array; a first insulating layer; and a passivation film. The memory cell array includes first interconnect layers and a first memory pillar. The first interconnect layers extend in a first direction substantially parallel to a semiconductor substrate. The first memory pillar passes through the first interconnect layers and extends in a second direction substantially perpendicular to the semiconductor substrate. The first insulating layer is provided above the memory cell array. The passivation film is provided on the first insulating layer, and includes a protrusion at least above the memory cell array and between the passivation film and the first insulating layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 24, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Gin Suzuki, Hiroki Yamashita, Yuichiro Fujiyama, Takuji Ohashi
  • Patent number: 11099927
    Abstract: According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: August 24, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Sato, Kenichiro Suzuki
  • Patent number: 11099736
    Abstract: A device and method dynamically optimize processing of a storage command within a storage system. The device and method execute a rule based on predetermined criteria and internal operation parameters of the storage system. An extended application program interface within the storage system provides internal operation parameters for use in execution of the rule. Based on execution of the rule, the storage system controls processing of the storage command.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 24, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Yaron Klein
  • Patent number: 11100999
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: August 24, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Patent number: 11093137
    Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 17, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 11096087
    Abstract: According to one embodiment, a control device includes one or more processors. The one or more processors receive a message. The one or more processors determine whether the received message has been replicated and transmitted. The one or more processors instruct recording of difference information between a message before replication and the received message when it is determined that the received message has been replicated and transmitted.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 17, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takahiro Yamaura, Masataka Goto
  • Publication number: 20210249083
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA
  • Patent number: 11088162
    Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Kotaro Fujii, Satoshi Nagashima, Yumi Nakajima
  • Patent number: 11086744
    Abstract: A memory system includes a first memory chip, and a controller that includes a first circuit, a second circuit, and a third circuit. The third circuit is configured to manage a first differential power consumption value that is a difference between first and second power consumption values. The first power consumption value is on first power that the first memory chip consumes while executing a first operation. The second power consumption value is on second power that the first memory chip consumes when suspending the first operation. The third circuit is configured to determine whether causing the first memory chip to suspend the first operation to execute a second operation is possible based on the first differential power consumption value.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinya Koizumi, Kouji Watanabe
  • Patent number: 11086775
    Abstract: According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. Each of the spaces is assigned to at least one write management area included in a nonvolatile memory. The write management area is a unit of an area which manages the number of write. The transmission unit transmits a command for the nonvolatile memory and identification data of a space assigned to a logical address space corresponding to the command.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Daisuke Hashimoto
  • Patent number: 11088164
    Abstract: According to one embodiment, a semiconductor memory device includes: first interconnect layers; a second interconnect layer separate from the first interconnect layers; a third interconnect layer separate from the first interconnect layers and adjacent to the second interconnect layer in a second direction; a first memory pillar which passes through the second interconnect layer; a second memory pillar which passes through the third interconnect layer. The second interconnect layer includes a first portion connected to a first contact plug. The third interconnect layer includes a second portion connected to a second contact plug. The first and second portions are arranged along a third direction which intersects the second direction.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Kojiro Shimizu
  • Patent number: 11086573
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Marie Takada, Masanobu Shirakawa, Tsukasa Tokutomi
  • Publication number: 20210240352
    Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tetsuya SUNATA, Daisuke Iwai, Kenichiro Yoshii
  • Publication number: 20210240345
    Abstract: A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 5, 2021
    Applicant: Toshiba Memory Corporation
    Inventor: Takuya FUTATSUYAMA
  • Publication number: 20210240355
    Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 5, 2021
    Applicant: Toshiba Memory Corporation
    Inventor: Takafumi ITO