Patents Assigned to Memory Technologies LLC
-
Patent number: 9208078Abstract: A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.Type: GrantFiled: October 21, 2014Date of Patent: December 8, 2015Assignee: Memory Technologies LLCInventors: Olli Luukkainen, Kimmo J. Mylly, Jani Hyvonen
-
Patent number: 9190165Abstract: The invention relates to a method comprising measuring the temperature of at least one location of a non-volatile memory; determining if said temperature measurement indicates that the data retention time of data stored at said at least one location is reduced below a threshold; and re-writing said data to said non-volatile memory in a response to a positive determination.Type: GrantFiled: February 9, 2015Date of Patent: November 17, 2015Assignee: Memory Technologies LLCInventors: Janne Tapani Nurminen, Kimmo J. Mylly, Matti Floman
-
Patent number: 9164804Abstract: A memory controller of a mass memory device determining that a memory operation has been initiated which involves the mass memory device, and in response dynamically checks for available processing resources of a host device that is operatively coupled to the mass memory device and thereafter puts at least one of the available processing resources into use for performing the memory operation. In various non-limiting examples: the available processing resources may be a core engine of a multi-core CPU, a DPS or a graphics processor; central processing unit; a digital signal processor; and a graphics processor; and it may also be dynamically checked whether memory resources of the host are available and those can be similarly put into use (e.g., write data to a DRAM of the host, process data in the DRAM with the host DSP, then write the processed data to the mass memory device).Type: GrantFiled: June 20, 2012Date of Patent: October 20, 2015Assignee: Memory Technologies LLCInventors: Matti Floman, Kimmo Mylly
-
Patent number: 9117531Abstract: A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed.Type: GrantFiled: February 28, 2014Date of Patent: August 25, 2015Assignee: Memory Technologies LLCInventors: Matti Floman, Kimmo J. Mylly
-
Patent number: 9116820Abstract: The specification and drawings present a new apparatus, method and software related product for using a cache/central cache module/device (instead of e.g., system DRAM) which can serve multiple memory modules/devices. Each memory/IO module/device connected to the same memory network (e.g., via hub, bus, etc.) may utilize memory resources of this cache module/device either in a fixed manner using pre-set allocation of resources per the memory module/device, or dynamically using run-time allocation of new resources to an existing module/device per its request or to a new module/device connecting to the memory network (e.g., comprised in a host device) and possibly requesting memory resources.Type: GrantFiled: August 28, 2012Date of Patent: August 25, 2015Assignee: Memory Technologies LLCInventor: Kimmo J. Mylly
-
Patent number: 9069663Abstract: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A performance ranking of a particular memory bank may be based at least in part on both a busyness and a row hit ratio of the particular memory bank. Apparatus and computer readable media are also described.Type: GrantFiled: July 23, 2014Date of Patent: June 30, 2015Assignee: Memory Technologies LLCInventors: Eero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara
-
Patent number: 9063850Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.Type: GrantFiled: July 25, 2013Date of Patent: June 23, 2015Assignee: Memory Technologies LLCInventors: Jani Hyvonen, Kimmo J. Mylly, Jussi Hakkinen, Yevgen Gyl
-
Patent number: 8982653Abstract: The invention relates to a method comprising measuring the temperature of at least one location of a non-volatile memory; determining if said temperature measurement indicates that the data retention time of data stored at said at least one location is reduced below a threshold; and re-writing said data to said non-volatile memory in response to a positive determination.Type: GrantFiled: November 11, 2008Date of Patent: March 17, 2015Assignee: Memory Technologies LLCInventors: Janne Tapani Nurminen, Kimmo Juhani Mylly, Matti Kalevi Floman
-
Patent number: 8874824Abstract: A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.Type: GrantFiled: June 4, 2009Date of Patent: October 28, 2014Assignee: Memory Technologies, LLCInventors: Olli Luukkainen, Kimmo Mylly, Jani Hyvonen
-
Patent number: 8867631Abstract: A method for wireless data communication between a wireless device having means for short-range data communication, and an electronic device includes mounting a data communication device having means for short-range radio frequency wireless data communication in a general purpose expansion memory location of the electronic device, activating a short-range radio frequency wireless data communication link between the wireless device and the data communication device, and transmitting data between the electronic device and the wireless device so that the wireless device operates as an ordinary expansion memory from the view point of the electronic device.Type: GrantFiled: March 19, 2007Date of Patent: October 21, 2014Assignee: Memory Technologies LLCInventors: Sami Inkinen, Simo Vapaakoski
-
Patent number: 8856488Abstract: Apparatuses and methods for implementing partitioning in memory cards and modules where conventional memory cards or modules have only a single partition. A representative memory card/module in accordance with the invention includes a memory device(s), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module further includes a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module includes means for controlling the partitioning of the memory device(s), and the memory controller is configured to operate the memory device(s) in accordance with the partition information.Type: GrantFiled: January 7, 2013Date of Patent: October 7, 2014Assignee: Memory Technologies LLCInventors: Yevgen Gyl, Jussi Hakkinen, Kimmo J. Mylly
-
Publication number: 20140247682Abstract: Reliability of a power supply is assessed, such as for example considering one or more of the following: whether a host device is experiencing fast acceleration; whether a portable power supply has sufficient energy to meet current needs; whether a battery or removable memory cover is in place; and whether a software failure within the host device is imminent. In dependence on the assessed reliability, there is a selection made between a first mode and a second mode for operating a mass memory. The first mode comprises better data retention than the second mode for the case that the power supply is interrupted, and the second mode comprises faster data transfer than the first mode for the case that the power supply is not interrupted. In one embodiment the first and second mode buffers write data utilizing respective non-volatile (flash) and volatile (DRAM) memory.Type: ApplicationFiled: May 16, 2014Publication date: September 4, 2014Applicant: Memory Technologies LLCInventor: Mikko Sami Tapani Kursula
-
Patent number: 8819379Abstract: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A performance ranking of a particular memory bank may be based at least in part on both a busyness and a row hit ratio of the particular memory bank. Apparatus and computer readable media are also described.Type: GrantFiled: November 15, 2011Date of Patent: August 26, 2014Assignee: Memory Technologies LLCInventors: Eero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara
-
Patent number: 8775847Abstract: Reliability of a power supply is assessed, such as for example considering one or more of the following: whether a host device is experiencing fast acceleration; whether a portable power supply has sufficient energy to meet current needs; whether a battery or removable memory cover is in place; and whether a software failure within the host device is imminent. In dependence on the assessed reliability, there is a selection made between a first mode and a second mode for operating a mass memory. The first mode comprises better data retention than the second mode for the case that the power supply is interrupted, and the second mode comprises faster data transfer than the first mode for the case that the power supply is not interrupted. In one embodiment the first and second mode buffers write data utilizing respective non-volatile (flash) and volatile (DRAM) memory.Type: GrantFiled: December 14, 2010Date of Patent: July 8, 2014Assignee: Memory Technologies LLCInventor: Mikko Sami Tapani Kursula
-
Publication number: 20140181382Abstract: A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed.Type: ApplicationFiled: February 28, 2014Publication date: June 26, 2014Applicant: Memory Technologies LLCInventors: Matti Floman, Kimmo J. Mylly
-
Publication number: 20140108701Abstract: Some implementations may include a memory management system in a virtualized environment that includes a virtual address, a virtual machine exposed by a virtual machine monitor, a translation lookaside buffer to store virtual address to physical address translations, and a memory protection unit to verify whether a physical address obtained from the virtual address is within boundaries of one or more physical system memory regions assigned to a virtual machine.Type: ApplicationFiled: December 16, 2013Publication date: April 17, 2014Applicant: MEMORY TECHNOLOGIES LLCInventor: Mika Pekka Liljeberg
-
Patent number: 8671240Abstract: A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed.Type: GrantFiled: July 18, 2011Date of Patent: March 11, 2014Assignee: Memory Technologies LLCInventors: Matti Floman, Kimmo Mylly
-
Patent number: D710441Type: GrantFiled: April 17, 2013Date of Patent: August 5, 2014Assignee: Mastermind Memory Technologies LLCInventor: Carrie A. Soler
-
Patent number: RE45486Abstract: The present invention relates to a method for addressing the memory locations of a memory card. There are several memory locations in a memory card for storing data, in which case in order to address a specific memory location an address is formed. At least one parameter is stored in the memory card, on the basis of which parameter the number of memory locations of a memory card can be calculated, and a specific number of bits is reserved for said at least one parameter. In the method, two or more memory locations are addressed with one address, and/or the number of bits that can be used in an address is increased. The invention also relates to a system and a memory card in which the method is applied.Type: GrantFiled: May 24, 2013Date of Patent: April 21, 2015Assignee: Memory Technologies LLCInventors: Marko Ahvenainen, Kimmo Mylly
-
Patent number: RE45542Abstract: The present invention relates to a method and a system for determining the power consumption in an electronic device, to which a peripheral device is connected, to which the power is supplied from the electronic device. At least a first maximum value and a second maximum value, higher than the first maximum value, are determined for the power consumption. Signaling between the electronic device and the peripheral device sets a maximum value for the power consumption of the peripheral device which is between said first and second maximum values. The invention also relates to an electronic device and a peripheral device, in which the method is applied.Type: GrantFiled: May 24, 2013Date of Patent: June 2, 2015Assignee: Memory Technologies LLCInventor: Kimmo Mylly