Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising vertically-alternating insulative tiers and conductive tiers directly above a conductor tier. Channel-material-string constructions of memory-cell strings extend through the insulative and conductive tiers. The channel material of the channel-material-string constructions directly electrically couples with conductor material of the conductor tier. The vertical stack comprising a memory-cell region comprises memory cells. Individual of the insulative tiers in the memory-cell region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being void space. The vertical stack comprises an upper region directly above the memory-cell region. The upper region comprises at least two of the conductive tiers and that comprise upper select gates.

Abstract: Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Abstract: An example apparatus includes a second bit line pair for substituting for a defective one of first bit line pairs, a sense amplifier circuit configured to amplify a potential difference between the second bit line pair, first and second local I/O lines coupled to the second bit line pair via a column switch, a sub-amplifier circuit configured to drive a main I/O line based on a potential difference between the first and second local I/O lines, a precharge circuit configured to precharge the first and second local I/O lines to a first power potential responsive to a first control signal, and a discharge circuit configured to discharge the second local I/O line to a second power potential different from the first power potential responsive to a second control signal.

Abstract: An apparatus that includes a plurality of first memory mats each including a plurality of common column sections except for at least one associated column section, the at least one associated column sections being selected by respective column addresses which are different from one another; and a second memory mat including the at least one corresponding column sections therein.

Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.

Abstract: Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described. A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.

Abstract: On-die temperature control for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor device assembly includes first and second semiconductor dies directly bonded to each other. The semiconductor dies each includes conductive pads and resistive heating components in a dielectric layer, where the resistive heating components are located proximate to the conductive pads to supply localized thermal energy to the conductive pads in response to electric current flowing through the resistive heating components. In some embodiments, the conductive pads of the first semiconductor die are directly bonded to the conductive pads of the second semiconductor die at a first temperature less than a second temperature for the thermal expansion of the conductive pads absent the localized thermal energy generated by the resistive heating components.

Abstract: Memory with fail indicators, and associated systems, devices, and methods are disclosed herein. In one embodiment, a system includes a plurality of memory systems and a host device. At least one of the memory systems includes a fail indicator connected to the host device via a side channel of the system. The host device is configured to detect an occurrence of a failure on the at least one memory system and to initiate activation of the fail indicator. The side channel can be an I2C or I3C® side channel. The fail indicator, when activated, can provide a visual indication of the failure. For example, the fail indicator can include an LED that can be activated to emit light and provide an indication of the failure. A color of the light can correspond to a type, occurrence, or location of the failure on the at least one memory system.

Abstract: Exemplary methods, apparatuses, and systems including a device health manager for managing health of a memory device. The device health manager identifies a memory device having a service life. The device health manager receives multiple requests to perform one or more computing operations. The device health manager predicts, using a machine learning model, an adjustment of the service life of the memory device using the health data. The device health manager generates a notification including the adjustment of the service life.

Abstract: Methods, systems, and devices for improved performance in a fragmented memory system are described. The memory system may detect conditions associated with a random access parameter stored at the memory system to assess a level of data fragmentation. The memory system may determine that a random access parameter, such as a data fragmentation parameter, a size of information associated with an access command, a depth of a command queue, a delay duration, or a quantity of commands satisfies a threshold. If one or more of the random access parameters satisfies the threshold, the memory system may transmit a request for the host system to increase an associated clock frequency. The host system may increase the number of commands sent to the memory system in a duration of time. That is, the host system may compensate for a slow-down due to data storage fragmentation by increasing the command processing rate.

Abstract: A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

Abstract: Near-cache compute can be implemented by a device that includes an interface configured to communicate with external entities and processing circuitry configured to receive a recall count request, from an entity on the interface. Here, the recall count request can specify a data object that is represented by a set of cache lines on the device. The device can tabulate a number of cache lines in the set of cache lines that are inconsistent to create a recall count and communicate a response to the entity via the interface that includes the recall count.

Abstract: Methods, systems, and devices for error detection and classification are described. A memory device may read a codeword from a memory and generate a first set of syndrome bits for the codeword. The memory device may use the first set of syndrome bits to generate a first error detection bit. The memory device may generate a second set of syndrome bits for the codeword and use the second set of syndrome bits to generate a second error detection bit. The memory device may provide the first error detection bit and the second error detection bit to a host device.

Abstract: Disclosed in some examples are methods, systems, devices, and architectures which provide for techniques for memory device and memory fabric redundancy within distributed memory systems. In some examples, two memory devices are paired and each stores a same set of data such that writes to the memory devices are duplicated and reads may be satisfied from either device. In some examples, a memory processing unit (MPU) may be incorporated into the memory architecture to support these paired memory devices. The MPU may be placed between the host and a multi-planed memory fabric which connects to multi-ported CXL memory devices. In some examples, the MPU may also enable the use of alternative fabric links. That is, if a memory fabric link between the MPU and a memory device is unavailable, an alternative link may be utilized to restore connectivity to a memory device.

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

Abstract: Methods, systems, and devices for read margin health evaluations for memory systems are described. A memory system may evaluate a read margin health for a set of memory cells (e.g., a page of memory cells, a block of memory cells) based on quantities of memory cells that activate in response to applying voltages to the set of memory cells. For example, the memory system may determine, for a pair of bias voltages between a first nominal voltage associated with a first logic state and a second nominal voltage associated with a second logic state, a respective quantity of memory cells of the set of memory cells that are activated in response to biasing the set of memory cells with each of the pair of voltages. Based on the quantities of activated memory cells, the memory system may determine whether to refresh the set of memory cells.

Abstract: Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).

Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

Abstract: System and techniques for synchronized request handling at a memory device are described herein. A request is received at the memory device. Here, the request indicates a memory address corresponding to a set of cache lines and a single cache line in the set of cache lines. The memory device maintains a deferred list for the set of cache lines and a set of lists with each member of the set of lists corresponding to one cache line in the set of cache lines. The memory device tests the deferred list to determine that the deferred list is not empty and places the request in the deferred list.