Abstract: Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.

Abstract: A system and method for memory error detection and recovery in a decoding system in CXL components is presented. The method includes receiving, into a first decoder within the decoding system, a memory transfer block (MTB) having data and parity information, and having a vertical portion and a horizontal portion, performing error detection and correction on the vertical portion of the MTB using binary hamming code logic within the first decoder; and upon performing error detection and correction in the first decoder, then forwarding MTB to a second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the MTB using a non-binary hamming code logic within the second decoder such that the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the MTB in a serial manner.

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

Abstract: Apparatuses and methods for on-device error correction implemented in a memory. A memory may have a first column plane comprising a first number of bit lines and a parity column plane that has a second number of parity bit lines in which the first number is different than the second number. In an access operation, a column select signal may activate the first number of bit lines in the first column plane and the second number of parity bit lines in the second column plane.

Abstract: The present disclosure relates to signal processing systems that employ various techniques to enhance data transfer quality. In some cases, a memory controller uses a neural network (e.g., time delay neural network (TDNN) to enable nonlinear processing to improve equalization. In some other cases, the memory controller uses an activation function to enable nonlinear processing to improve equalization. The systems may incorporate a finite impulse response (FIR) filter with the activation function applied to its output. A memory controller including a cache may store precomputed values of the activation function. Various types of activation functions or neural network configurations may be employed to introduce nonlinearity and adapt to different application requirements. The present disclosure is applicable in communication systems, control systems, and other digital signal processing systems requiring efficient processing of complex data transmission patterns.

Abstract: Apparatus might include a plurality of series-connected first field-effect transistors selectively connected in series with a plurality of series-connected second field-effect transistors, wherein the plurality of series-connected first field-effect transistors are configured to store user data, and wherein a channel of the plurality of series-connected second transistors is capacitively coupled to a channel of a third transistor.

Abstract: According to one or more embodiments of the disclosure, an apparatus comprises a plurality of core chips that includes a plurality of spiral through-substrate vias (TSVs). The core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other, of the plurality of core chips. The first core chip and the second core chips include a first function circuit and a second function circuit coupled to the first function circuit, respectively. The first function circuit and the second function circuit provide a first clock divider circuit and a second clock divider circuit, respectively. The first and second clock divider circuits are activated to jointly provide a clock division function.

Abstract: An example of compute express link (CXL) system includes a memory, and a tensor access circuit having a memory mapper configured to configure a memory map based on a compute express link (CXL) command associated with an access operation of the memory. The memory map includes a specific sequence of CXL instructions to access to the memory via a CXL bus.

Abstract: A memory includes a receiver circuit configured to receive write data via a data terminal, and a neural network based preconditioning circuit configured to receive a write data signal according to the write data. A neural network of the preconditioning circuit is configured to precondition the write data signal based on a characteristic of a write data path to provide a modified write data signal. The memory further includes a memory array configured to store the write data based on the modified write data signal.

Abstract: The present invention relates to a memory controller and a memory device that are configured to communicate with each other using multiple input multiple output (MIMO) technology. The memory controller includes a precoder that precodes data for transmission. The precoding is based on channel state information, a neural network, or both. The memory device receives the precoded data and decodes them to retrieve the original data. In some cases, the precoder uses the channel state information to optimize the precoding matrix for the given channel conditions. In some cases, a neural network is trained to predict the optimal precoding matrix for the current channel state. The precoding matrix is then used to encode the data, which is then transmitted to the memory device. The use of MIMO and precoding improves the reliability and efficiency of the communication between the memory controller and memory device.

Abstract: According to one or more embodiments of the disclosure, an apparatus comprises a plurality of core chips that includes a plurality of spiral through-substrate vias (TSVs). The core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other, of the plurality of core chips. The first core chip and the second core chips include a first function circuit and a second function circuit coupled to the first function circuit, respectively. The first function circuit and the second function circuit provide the same functions.

Abstract: According to one or more embodiments of the disclosure, an apparatus comprises a plurality of core chips that includes a plurality of spiral through-substrate vias (TSVs). The core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other, of the plurality of core chips. The first core chip and the second core chips include a first function circuit and a second function circuit coupled to the first function circuit, respectively. The first function circuit and the second function circuit provide a logic circuit and a power supply circuit, respectively. The logic circuit receives power from the power supply circuit.

Abstract: Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising responsive to receiving a memory access command, determining a portion of the memory device that is referenced by a logical address specified by the memory access command; determining an endurance factor associated with the portion; and modifying, based on a value derived from the endurance factor, a media management metric associated with the portion of the memory device.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on memory component reliabilities. The controller can access configuration data to determine a reliability grade associated with individual groups of the memory components. The controller can then adaptively select between different media management operations based on the reliability grade associated with each individual group of the memory components.

Abstract: Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.

Abstract: An example method of performing read operation comprises: receiving a read request with respect to a set of memory cells of a memory device; determining a value of a media endurance metric of the set of memory cells; determining a programing temperature associated with the set of memory cells; determining a current operating temperature of the memory device; determining a voltage adjustment value based on the value of the media endurance metric, the programming temperature, and the current operating temperature; adjusting, by the voltage adjustment value, a bitline voltage applied to a bitline associated with the set of memory cells; and performing, using the adjusted bitline voltage, a read operation with respect to the set of memory cells.

Abstract: Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.

Abstract: Disclosed in some examples are methods, systems, memory devices, memory controllers, and machine-readable mediums which provide for reserving physical memory device resources to specific execution units. Execution units may include processes, threads, virtual machines, functions, procedures, or the like. Physical memory device resources may include channels, modules, ranks, banks, bank groups, and the like. For example, a physical memory device resource that is reservable may be a smallest unit that allows for parallel access with another of the same size unit.