Abstract: A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.

Abstract: A processing device in a memory sub-system identifies an indication of a completion of a memory access command directed to a memory device and determines whether there are other memory access commands directed to the memory device that are pending. Responsive to determining that there are other memory access commands pending, the processing device coalesces additional indications of completions of the other memory access commands that are available within a threshold period of time with the indication of the completion into a completion data chunk and sends the completion data chunk to a host system. The host system is to store the completion data chunk as one or more completion queue entries in a completion queue in a host memory of the host system via a single host memory write operation.

Abstract: Apparatuses and techniques for efficient handling of data errors and usage-based disturbances are described. To enable efficient utilization of time-limited resources, a memory device includes control circuitry that performs multiple different types of operations responsive to “confiscating” a refresh-pump time interval. The memory device is responsible for performing various functionalities internally while reducing the impact such functionalities may have on servicing memory requests from an external entity. Accordingly, a memory device may confiscate refresh-pump opportunities and instead perform other operations. To efficiently utilize a refresh-pump opportunity, the control circuitry can perform an error-handling operation on a codeword stored in a first bank and perform a usage-based disturbance mitigation operation on a row in a second bank during the confiscated time interval. Further, the usage-based disturbance mitigation operation can be performed across multiple banks except for the first bank.

Abstract: Systems, methods, and apparatus for a memory device that uses multiple groups of pattern cells to select a voltage for reading memory cells. In one approach, a controller applies different magnitude levels of voltages to each of the groups of pattern cells. The controller determines which of the groups have pattern cells that first switch (e.g., switch at the lowest magnitude of applied voltage). Based on identifying the first group to switch, the controller selects a read voltage. The selected read voltage is used to read data cells (e.g., corresponding to a codeword).

Abstract: Apparatuses, systems, and methods for per row error correct and scrub (pRECS) registers. A mode register may include a pRECS enable register, to enable a pRECS mode. When the prECS mode is enabled, pRECS information associated with each row may be collected which reflects a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row. A pRECS address register may specify a location in the memory array to store the pRECS information.

Abstract: A system and method are disclosed for decoding hard data from a memory device. For example, a controller performs a read operation to receive hard data from the memory device. The controller converts the hard data into soft information. The controller can decode using a first decoder for a first number of decoding iterations based on the soft information. An error vector indicating which bits of the hard data have been flipped by the first decoder can be generated by the controller based on a current state of a codeword for a respective decoding iteration of the first number of decoding iterations. The controller can decode using a second decoder to correct errors in the hard data for a second number of decoding iterations based on the error vector and the original hard data. The controller can provide corrected data in response to correcting the errors in the hard data.

Abstract: A method for performing a media scan operation in a memory device is described herein. The method includes initiating the media scan operation via a controller. The method also includes selecting one or more codewords that is a proper subset of a plurality of codewords in a page of memory via the controller. The method also includes determining a bit error count (BEC) of each of the one or more codewords via the controller. The method also includes comparing the BEC of each of the one or more codewords with a BEC threshold via the controller. The method further includes determining the BEC of each of the codewords of the page of memory via the controller in response to the BEC of one or more of the selected set of codewords being greater than the BEC threshold.

Abstract: Methods, systems, and devices for data path signal amplification in coupled semiconductor systems are described. A semiconductor system may implement a first die including memory arrays and a second die including a host interface. The first die may include a first portion of a data path between the memory arrays and the host interface, including a first portion of data path signal amplification circuitry. The second die may include a second portion of the data path, including a second portion of data path signal amplification circuitry. The semiconductor system may implement fine-pitch interconnection between dies to support a relatively greater quantity of signal paths of the data path which, in some examples, may support reducing or eliminating serialization/deserialization circuitry associated with coarser interconnection. In some implementations, a semiconductor system may implement a switching component operable to switch between data paths having different amplification configurations of the dies.

Abstract: Methods, systems, and devices for techniques to improve boot up latency of a memory system are described. As one example of the methods, a memory system may receive an indication to perform a power down operation and write, based on the indication, information corresponding to the power down operation to a first block of memory cells used to store bad block information. Further, the memory system may perform the power down operation based on writing the information corresponding to the power down operation to the first block of memory cells.

Abstract: An asymmetric search can be performed by providing a first access command, for a first address of a target memory device, to a first bin of the target memory device, where the target memory device includes a plurality of ports and the first access command is provided to the first bin utilizing a first port. A second access command, for a second address of the target memory device, can be provided to a second bin of the target memory device. The second address can have a first offset from the first address. The second access command can be provided to the second bin utilizing a second port from the plurality of ports. The first access command and the second access command can be provided by an initiator device to the first bin and the second bin via a fabric that connect the initiator device to the target memory device.

Abstract: A method includes generating parity data corresponding to a plurality of word lines coupled to blocks of a memory device and generating additional parity data for a block based on a physical location of the block. The method can further include performing a data recovery operation based on the parity data, the additional parity data, or a combination thereof.

Abstract: Methods, systems, and devices for segregating logical to physical mappings are described. A memory system may segregate L2P mappings based on one or more characteristics of the data associated with to the L2P mappings. The memory system may determine whether a logical address included in a write command is associated with a first characteristic, a second characteristic, or some other characteristic. The memory system may write an L2P mapping to a first block of memory cells, a second block of memory cells, or some other block of memory cells based on the determined characteristic of the L2P mapping. The block of memory cells that the L2P mapping is written to may include other mappings having data with a same (or similar) characteristic.

Abstract: A method for monitoring health of a die in a memory device and dynamically adjusting a device parameter. The method includes receiving a request for performing a memory access operation on a first data unit of a memory device, and determining a value of a media state metric of the first data unit. The method further includes modifying a device parameter of the first data unit to form a modified device parameter in response to determining that the value of the media state metric of the first data unit is greater than a predetermined threshold value, and performing, using the modified device parameter, the memory access operation on the first data unit.

Abstract: A memory sub-system having non-volatile media on which multiple namespaces are allocated. A command from a host system has an identification of a namespace and at least one error recovery parameter. A controller of the memory sub-system configures the namespace on the non-volatile media according to the at least one error recovery parameter, stores the at least one error recovery parameter in association with the namespace, and controls error recovery operations for data access in the namespace in accordance with the at least one error recovery parameter stored in association with the namespace.

Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

Abstract: A microelectronic device comprises a stack structure comprising blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers, at least one of the blocks comprising: a memory array region having vertically extending strings of memory cells within a horizontal area thereof; and a staircase region horizontally neighboring the memory array region. The staircase structure has steps comprising horizontal ends of the tiers; and a crest sub-region horizontally interposed between the staircase structure and the memory array region. A masking structure overlies the stack structure and has a different material composition than each of the conductive material and the insulative material. Filled slot structures are interposed between the blocks of the stack structure, at least one of the filled slot structures comprises at least one fill material that has an uppermost boundary vertically underlying an uppermost boundary of the masking structure.

Abstract: A semiconductor device can include a substrate of semiconductor material and multiple stacks of memory cells disposed within the substrate. Each of the stacks can include a conductive string that connects memory cells to a bitline where each memory cell is located at an intersection of the conductive string and a wordline. The device can also include capacitor having a cylindrical body disposed between two adjacent stacks of memory cells where the capacitor includes an inner conductive layer and an outer conductive layer at least partially surrounding the inner conductive layer, where the inner conductive layer and the outer conductive layer are separated by a dielectric layer. The device can further include a power supply line conductively connected to an end of the capacitor at a base of the cylindrical body.

Abstract: Methods, systems, and devices for program failure handling in non-volatile memory systems are described. The memory system may identify a program failure associated with writing data to a first address of a first block of memory cells. The memory system may move data from the first block to a second block of memory cells based on identifying the program failure at the first address. The memory system may alter the data stored to the second block to include an uncorrectable error after moving the data from the first block. The memory system may perform a redundant array of independent NAND (RAIN) operation on the altered data stored to the second block. In some examples, the RAIN operation may include correcting the uncorrectable error stored to the second block and moving the data from the second block to a third block of memory cells.

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction

Abstract: Methods, systems, and devices for memory device health monitoring logic are described. In accordance with examples as disclosed herein, a memory device may include health monitoring logic configured to monitor a degradation level of the memory device. Further, the health monitoring logic may include a self-check logic to monitor the degradation level of the health monitoring logic. Using the health monitoring logic, the memory device may evaluate and store a health state of the memory device, which may be used to flag a fault in the memory device, among other responsive operations. Additionally, using the self-check logic, the memory device may evaluate and store a health state of the health monitoring logic, which may be used to flag a fault of the previously evaluated health state of the memory device. Based on the self-check flag, a host device may halt or adjust the response operations associated with the memory device.