Abstract: A system includes a first wireless communication device comprising a first baseband processor neural network configured to process at least part of data for transmission to a second wireless communication device according to a collaborative processing configuration while collaborative processing is enabled to generate a first radio frequency (RF) signal. The first wireless communication device is configured to transmit the first RF signal. The system further includes a third wireless communication device comprising a second baseband processor neural network configured to, while the collaborative processing is enabled, process at least part of the data for transmission to the second wireless communication device according to a collaborative processing configuration to generate a second RF signal. The third wireless communication device is configured to transmit the second RF signal in collaboration with transmission of the first RF signal by the first baseband processor.

Abstract: Apparatuses and techniques for implementing refresh latency indication for refresh operations are described. A memory system may separate memory dies into different ranks. Sending separate refresh commands to each rank congests the command bus. Sending a common refresh command to multiple ranks, on the other hand, causes a large current spike as many dies initiate the refresh operation at the same time. To efficiently prevent the large current spike and thereby lower the costs of a power delivery network, different dies can delay initiation of the refresh commands by different amounts. To do so, a host device can program different dies with different refresh latency indications, which determine lengths of each delay period before starting the refresh operation. The dies can also operate based on an enablement indication that enables the refresh latency mechanism. Staggering the start times of refresh operations can also control current spikes without regard to ranks.

Abstract: Apparatuses and techniques for reporting a notification-type event are described. In an example aspect, a memory device includes a dedicated notification pin for reporting one or more notification-type events to a memory controller. Through the notification pin, the memory device can indicate an occurrence of various notification-type events, one or more of which can be associated with mitigating usage-based disturbance. In contrast to an alert pin, the notification pin enables an operation of the memory controller to continue uninterrupted. In other words, notification-type events that are reported via the notification pin do not need to interrupt an operation of the memory controller. In this way, the notification pin can be used to communicate notifications without degrading performance of the memory controller. Also, with a dedicated notification pin, the memory controller can avoid continuously polling mode registers of the memory device for information, thereby conserving power and temporal resources.

Abstract: Systems and methods of independent thermal control of devices under test (DUTs) (e.g., memory devices) are disclosed herein. DUTs are coupled to dedicated cooling channels that include one or more controllable fans. The fans can be controlled independently according to temperature information of the DUTs, which is typically measured by an internal temperature sensor disposed in the DUTs. The fans of the cooling channels can be top-mounted (e.g., downdraft), bottom-mounted (e.g., updraft), or mounted on the front side of a DUT. Each cooling channel also has an exhaust channel on the front, top, and/or bottom of the channel for releasing heat. Advantageously, the air in the channel is guided by a shroud or cover placed over the DUT that can include internal vectored louvres, ridges, fins, ducts, chambers, etc., for directing air across surfaces of the DUT to evenly and efficiently cool the DUT during testing.

Abstract: A processing device, operatively coupled with a memory device, performs a first sequence of programming operations on a first set of cells addressable by a first wordline of the memory device. The processing device identifies a second wordline of the memory device, wherein a second physical location of the second wordline is in a predefined relationship with a first physical location of the first wordline. The processing device performs a second sequence of programming operations on a second set of cells addressable by the second wordline of the first die, wherein a first order of the first sequence of programming operations is different from a second order of the second sequence of programming operations.

Abstract: A processing device includes flash translation layer logic to be coupled to a memory device and that includes cursor logic to generate a criteria set associated with generating a backend command to be sent the memory device and streamer logic to access and employ the criteria set, e.g., aggregates translation units (TUs) received in one or more write messages. The criteria set enables accessing the plurality of TUs within a first format, of the one or more write messages, that depends on a data path associated with the one or more write messages. The streamer logic formats the aggregated TUs into the backend command having a second format for transmittal to the memory device. The backend command is to direct the memory device in writing TU data, associated with the TUs, to a memory array of the memory device.

Abstract: Methods, systems, and devices for establishing memory system read window budget (RWB) are described. A memory system may receive a command from a host system requesting an RWB for an edge of a distribution of a logic level of a set of logic levels. The memory system may determine an expected pattern of data corresponding to a set of memory cells and may store the expected pattern in memory. The memory system may perform a voltage sweep operation, including setting a read voltage to different levels across the edge for reading the set of memory cells. The memory system may count a quantity of expected bits resulting from a logic function of the expected pattern and the read data for each level, and may output a voltage offset corresponding to level at which a difference of the quantity of expected bits and an initial quantity satisfies a threshold.

Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first sub-block of a first die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks. The processing device identifies, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device. The processing device further performs the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.

Abstract: Methods, apparatuses, and systems related to operations for measuring the quality of a signal received by a memory device and providing feedback. The memory device can sample signal data using a predetermined sequence of timing offsets relative to a reference signal. Additionally or alternatively, the memory device can sample the signal data using a predetermined sequence of reference voltages. The memory device can provide feedback results to a controller regarding the quality of the sampled signal data.

Abstract: A buffer management component of a memory sub-system configures buffers in a data path associated with a memory device. Available buffers are enabled to store memory associated with an address of the memory device. The buffer management component receives a first command pertaining to a first address of the memory device; responsive to receiving the first command, initiates a first memory operation at the first address using a first available buffer; receives a second command pertaining to a second address of the memory device before the first command has been completed; and responsive to receiving the second command, initiates a second memory operation at the second address of the memory device using a second available buffer.

Abstract: Apparatuses and methods for determining performing read operations on a partially programmed block are provided. One example apparatus can include a controller configured to apply a read voltage to a word line in an array of memory cells during a read operation on the word line, apply a first pass voltage to a number of programmed word lines in the array of memory cells during the read operation, and apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells during the read operation.

Abstract: Disclosed in some examples are methods, systems, and machine-readable mediums which utilize augmented reality devices to detect and warn vulnerable individuals about real-life situations that could pose a hazard to their safety. One or more signals identified from data captured by sensors of one or more devices of the user may be analyzed to determine whether elements such as persons, objects, or the like pose a danger to the user. The system, upon detection of an unsafe event, situation, or person may then warn the user through the augmented reality glasses of the unsafe events, situations, or persons. In addition, a caregiver or other individual and/or the police may also be notified.

Abstract: A processing device calculates a set of reference system measurements based on an initial firmware image corresponding to a memory device. The processing device stores the set of reference system measurements in a measurement attestation block of the memory device. A set of current system measurements are calculated by the processing device based on a current firmware image corresponding to the memory device. The processing device performs a comparison of the set of current system measurements with the set of reference system measurements stored in the measurement attestation block of the memory device and performs an action with respect to the memory device based on a result of the comparison.

Abstract: Systems and methods for retaining data related to a detected collision are disclosed including receiving vehicle information from a sensor, receiving information about one or more other vehicles using a communication circuit, receiving an indication of a detected collision, and responsive to the received indication of the detected collision, storing information corresponding to the detected collision from a collision reenactment period in non-volatile memory of the first vehicle and broadcasting the information corresponding to the detected collision using the communication circuit.

Abstract: Control logic in a memory device initiates a loop of a program operation comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective programming levels and (b) a corresponding program verify phase. The control logic further identifies memory cells associated with a first sub-set of programming levels to be verified during the program verify phase, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level and a second lowest programing level. The control logic further performs concurrent sensing operations on the identified memory cells during the program verify phase to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor device including a plurality of electrical contacts on an upper surface thereof; a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface into a body of the monolithic silicon structure; and a second semiconductor device disposed in the cavity and including a plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts.

Abstract: A semiconductor device assembly is described that includes two semiconductor dies. The semiconductor dies each include a layer of dielectric material and a reservoir of conductive material located adjacent to openings in the layer of dielectric material. The opening at the layer of dielectric material of the first semiconductor die and the opening at the layer of dielectric material of the second semiconductor die are aligned to create an interconnect opening. The reservoirs of conductive material are heated to volumetrically expand the reservoirs of conductive material past one another such that they contact at respective non-horizontal surfaces to form an interconnect electrically coupling the semiconductor dies. In this way, a connected semiconductor device may be assembled.

Abstract: A respective bitmap of a set of bitmaps is divided into a plurality of logical pages and sequentially assigned a logical page number. A plurality of logical pages identified by a specified logical page number into a corresponding logical super-page is combined. A contiguous block of memory from a memory device of the plurality of memory device to the specified logical super-page is allocated. A mapping of the specified logical page number to a physical address of the contiguous block of memory is stored in a memory data structure. A request to initialize the set of ordered bitmaps is received. obtaining, from the memory data structure, A physical address associated with a respective logical page number is obtained from the memory data structure for each logical page number. A memory set operation on the contiguous block of memory associated with the physical address is performed.

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.