Abstract: An apparatus that includes a beamforming antenna is provided. The apparatus may include a predictive calculator processing unit to receive position information of one or more airborne receivers, determine future position information of the one or more airborne receivers as a function of time based on the received position information, and determine beamforming antenna parameters. The apparatus may include an antenna instruction processing unit to receive the beamforming antenna parameters and generate beamforming instructions based on the beamforming antenna parameters, a beamforming antenna to receive the beamforming instructions, and to generate a beam at a specified time based on the beamforming instructions to enable communication with at least one of the one or more airborne receivers, and a receiver processing unit to receive airborne receiver data from the at least one of the one or more airborne receivers, and generate output data based on the airborne receiver data.

Abstract: A Controller Area Network (CAN) bus driver for driving a CAN bus is provided. The bus driver may include a first translinear loop circuit to receive an input voltage and output a first output current signal corresponding to an exponential function, a second translinear loop circuit to receive the input voltage and output a second output current signal corresponding to a hyperbolic function, a divider circuit to output a divided output current signal corresponding to the first output current signal divided by the second output current signal, a CAN Lo driver circuit to output the divided output current signal to a CAN Lo wire of the CAN bus, and a CAN Hi driver circuit to output the divided output current signal to a CAN Hi wire of the CAN bus.

Abstract: A smart cable for backplane storage management is provided. The cable may include a microcontroller, a power conditioning circuitry to regulate an input voltage from a power supply and provide an output voltage to the microcontroller, a storage device coupled to the microcontroller, a first end to be coupled to one or more storage devices, and a second end to be coupled to a storage controller. The microcontroller may receive sideband signals from the one or more storage drives, and may transmit connection topology information to the storage controller based at least in part on the sideband signals.

Abstract: A computer-implemented method and media for efficient power management of a data storage device including: receiving a host read request, identifying a virtual block (VB) included in the data storage device based on the host read request; determining an open block state of the identified VB, and performing a read operation on the identified VB corresponding to the host read request based on the determined open block state of the identified VB.

Abstract: A Peripheral Trigger Generator (PTG) for generating signals adaptively responsive to time-driven events based on execution run time. A variable PTG step delay, such as a “wait for software trigger” command, may provide an adaptive step delay between the output trigger commands. An adaptive step delay may use a combination of PTG Command+Control Bit in PTG Special Function Register. The adaptive step delay may be part of the Functional Safety Diagnostics package developed for the PTG module.

Abstract: In some implementations, a controller may receive a command to perform an erase operation to erase data stored in a block of a non-volatile memory device. The controller may determine a size of the data identified by the command. The controller may provide, based on the size of the data, a programming pulse to a location, of the block, that stores the data, wherein the programming pulse is provided to write predetermined data at the location. The controller may perform an erase operation on the block after writing the predetermined data.

Abstract: A controller for a motor system includes an input terminal to receive a signal indicating a speed of an electric motor and a regenerative brake current interpolator to indicate a brake current to be applied to the electric motor responsive to the speed of the electric motor. Values of the brake current vary with variation of the speed of the electric motor.

Abstract: A data storage system includes a memory device, a memory including instructions stored thereon, and at least one processor. The memory device includes a block that may include a plurality of wordlines (WLs). The memory includes instructions stored thereon that, when executed by the at least one processor, cause the at least one processor to: identify a plurality of data retention temperatures determined for the block at a plurality of corresponding times; compute an adjusted pass-through voltage (Vpassr) based on the plurality of data retention temperatures; and perform a read operation at least in part by: applying a read voltage (Vread) to a selected WL of the plurality of WLs; and applying the adjusted Vpassr to one or more unselected WLs of the plurality of WLs.

Abstract: A computer-implemented method, media, and systems for monitoring the health of a data storage device by: aggregating, or collecting, aggregate health data of a plurality of data storage devices and modifying, based on the aggregate health date, an aspect of memory management by one or both of: enacting an operational change on at least one of the plurality of data storage devices, or making a responsibility assignment modification for one or more operations among the plurality of data storage devices.

Abstract: A data storage system includes a memory device and a controller. The memory device includes a set of planes and a wordline including a set of pages. The controller includes a first and second minimum write cache control buffer (mWCCBs), processor(s), and a memory. The memory includes instructions, that when executed the processor(s), cause the processor(s) to: determine that an amount of outstanding data of a data stream is not sufficient to occupy the set of planes; store a first portion of the outstanding data in the first mWCCB; release the first portion to the memory device; in coordination with the release of the first portion of the outstanding data, store a second portion of the outstanding data in the second mWCCB; release the second portion to the memory device; and write the first and second portions of the outstanding data to a subset of the set of pages.

Abstract: A method of manufacturing a vapor cell includes forming a body of the vapor cell having walls defining a cavity thereinbetween, the cavity having an amount of a subject material contained therein. The method also includes forming a pore structure having a substrate material with pores of a substantially uniform dimension formed therein, the pore structure disposed along a portion of one or more of the walls of the vapor cell. The method further includes forming a liner material of a uniform thickness over one or more internal surfaces of the pores, wherein the subject material exhibits a reduced wetting angle on the liner material which is less than a wetting angle of the subject material on the substrate material.

Abstract: A system and method for the addition of heat transfer particles in a vertical cavity surface emitting laser (VCSEL) are disclosed. The method may include adding a plurality of nanoparticles to a passivation material. The plurality of nanoparticles may have a thermal conductivity of less than 2,200 Watts per meter-Kelvin (W/m-K) at zero degrees Kelvin. The method may also include forming a passivation layer between an active region and a contact in a vertical cavity surface emitting laser. The passivation layer may include the passivation material and the plurality of nanoparticles.

Abstract: A system and method for an efficient method for creating a silicon on insulator (SOI) wafer are disclosed. The method may include coating an unpolished single-crystalline silicon wafer with a spin-on-glass to create a spin-on-glass layer. The method may also include growing an etch stop layer on a second single-crystalline silicon wafer. The method may additionally include growing a silicon layer on the etch stop layer. The method may include bonding the silicon layer to the spin-on-glass layer. The method may also include polishing back the second single-crystalline silicon wafer. The method may further include removing the etch stop layer to create a silicon on insulator (SOI) substrate.

Abstract: A method for making a three dimensional (3D) Metal-Insulator-Metal (MIM) capacitor and trenches by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein the deposited conformal metal forms bottom and sidewall portions of a 3D bottom electrode of a metal-insulator-metal (MIM) capacitor in the tub, and wherein the deposited conformal metal forms a via or contact in the via or contact hole; removing conformal metal and at least a portion of the dielectric layer from a lip of the tub; depositing an insulator layer on the 3D bottom electrode to form an insulator layer of the MIM capacitor; and depositing a metal layer on the insulator layer to form a top electrode of the MIM capacitor.

Abstract: A data storage system may include a memory device and a controller. The controller may include at least one processor and a memory. The memory may include instructions stored thereon, that when executed by at least one processor, cause the at least one processor to: assign memory spaces of the memory device respectively to corresponding ones of a plurality of data requestors, said memory spaces having corresponding physical addresses; receive data access requests from the plurality of data requestors; generate a queue of the data access requests for accessing the memory device; and responsive to the data access requests, enable the plurality of data requestors to directly access corresponding ones of the respective memory spaces.

Abstract: One or more examples relate, generally, to providing timing signals to gate drivers of a converter. An example apparatus for providing timing signals to gate drivers of a converter includes a circuit that includes a timing input, and a plurality of outputs. The timing input may receive an incoming timing signal. The plurality of outputs may couple to a respective plurality of gate drivers to control an output voltage of a converter. The circuit may provide respective timing signals, at respective ones of the plurality of outputs at least partially responsive to the incoming timing signal, the respective timing signals synchronized such that like edges of the respective timing signals coincide.

Abstract: Teachings of the present disclosure include systems and/or methods for encoding digital data into a handwritten sample. An example method includes: accessing a predetermined vibration pattern stored in a memory corresponding to defined data; and vibrating a stylus based on the predetermined vibration pattern during creation of the handwritten sample to encode the defined data into the handwriting sample.

Abstract: A High-Electron-Mobility-Transistor comprising an upper insulating layer formed over a third buffer layer formed over a third barrier layer formed over a second buffer layer formed over a second barrier layer formed over a first buffer layer formed over a first barrier layer formed over a first doped structure and formed over a substrate. A second doped structure formed within the third barrier layer. A first gate electrode connected to the first doped structure. A second gate electrode connected to the second doped structure. A drain terminal formed at a first side of the first gate electrode. A source terminal formed at a second side of the first gate electrode.

Abstract: An apparatus, system, and method for incorporating monitoring systems, e.g., smoke detectors, in pre-existing devices, e.g., a garage door opener, light switch, or electric outlet is disclosed. The apparatus may include an interface to a hazard detector. The hazard detector may have dimensions that fit substantially within a fixture installed in a wall or a ceiling of a building and attached to the fixture such that the hazard detector is contained substantially within the fixture, the fixture to serve a purpose unrelated to hazard detection. The apparatus may also include a control circuit. The control circuit may be configured to receive a signal from the hazard detector via the interface. The control circuit may also be configured to detect an unsafe condition based on the signal. The control circuit may further be to raise an alarm in response to the unsafe condition.

Abstract: A method of detecting an over-programming of a memory cell during a write operation in a non-volatile memory media of a solid-state drive, and a solid-state drive with over-programming detection. When data is written to the states of the memory cell, a current last bit is routinely or selectively checked to detect an over-programming condition of the current state. An over-programming verification level may be used to check the current last bit and may be between zero and twenty-five millivolts lower than a regular programming verification level for a next first bit of the next state. When the over-programming condition is not detected, the program operation continues to write data to the next state. When the over-programming condition is detected, either the over-programmed current last bit is identified and the program operation is adjusted, or a memory block in which the over-programmed current last bit is located is retired.