Abstract: One or more examples relate to an apparatus to amplify differential voltage signal components of voltage across a resistor. Such an apparatus may include a resistor; a differential amplification circuit operatively coupled with the resistor to amplify a differential voltage signal component of a voltage across the resistor; and an operative coupling between the resistor and the differential amplification circuit to pass the differential voltage signal component and isolate a common mode voltage signal component of the voltage across the resistor.

Abstract: An apparatus comprises an upstream hub port, a plurality of downstream hub ports, a hub controller, a device response memory accessible to the hub controller, and a routing system connecting (a) the upstream hub port to the plurality of downstream hub ports and (b) respective downstream hub ports to the hub controller. The routing system to communicate device responses from respective downstream hub ports to the hub controller. The hub controller includes hub controller circuitry to identify specified device data in a respective device response received from a respective downstream hub port, and store the specified device data in the device response memory.

Abstract: In some implementations, a storage device may perform a read operation using a first read voltage. The storage device may identify a read error associated with the read operation. The storage device may identify a difference between the first read voltage and a second read voltage, the second read voltage associated with a reduced raw bit error rate (RBER). The storage device may perform a write operation using a program verify voltage that is based on the difference.

Abstract: One or more examples of systems, methods and devices are disclosed for provisioning a headless WiFi device. A method may include: inferring a channel identifier of a desired WiFi router access point, establishing a communication link with a provisioning WiFi device utilizing the channel identifier, and establishing a communication link with the WiFi router access point utilizing a channel identifier provided by the provisioning WiFi device.

Abstract: Systems and methods to chain smaller non-contiguous free chunks in non-volatile memory to form a logical storage volume which is greater than any of the constituent free chunks. These comprise: identifying a plurality of free chunks of available storage in a storage array; identifying a start block offset and a number of blocks of respective ones of the plurality of free chunks; creating a logical volume by chaining the plurality of free chunks, wherein blocks are provisioned in the logical volume beginning at a first free chunk start block offset for a first free chunk number of blocks, continuing to provision blocks in the logical volume at a second free chunk start block offset for a second free chunk number of blocks, and continuing to provision blocks in the logical volume until the plurality of free chunks are provisioned in the logical volume.

Abstract: A computer-implemented method for increasing reliability of a NAND flash device, the method comprising performing, via a flash controller, the operations of determining a read error rate of a virtual block included in the NAND flash device; determining, based at least in part on the read error rate, that garbage collection should be performed on the virtual block; and performing, based on the determination that garbage collection should be performed, the garbage collection on the virtual block.

Abstract: A wireless communication device includes a communication element, non-transitory computer-readable storage media including instructions stored thereon, and at least one processor. The instructions, when executed by the at least one processor, cause the at least one processor to: transmit, by the communication element, a first signal; during a pre-defined time period following the transmission of the first signal, detect, by the communication element, a second signal; responsive to detecting the second signal, perform, during the pre-defined time period, a measurement; and determine path loss based on the measurement.

Abstract: Systems having a capacitive touch sensing system with transmit and receive electrodes positioned to have mutual capacitances at node intersections that deviate when a node is touched; a processor; and a machine readable storage medium with instructions to: assign complete code words to transmit electrodes; identify a subset of transmit electrodes based on a prior touch position estimate; generate a transmit signal for the transmit electrodes; receive a first portion of a receive signal for receive electrodes indicative of capacitances; decode the first portion of the receive signal of receive electrodes using the first portions of the code words; and compute touch position estimates for the subset of transmit electrodes based on the decoded first portions of the receive signals.

Abstract: As an example, an apparatus may include: an ionization chamber, a voltage source to drive the ionization chamber; a voltage sensor to measure an ionization chamber output voltage; a calibration circuit to compensate the ionization chamber output voltage based on a correction factor; and a monitoring circuit to trigger an alarm if the compensated output voltage meets a predetermined condition. The calibration circuit may determine the correction factor to compensate for any leakage current affecting the ionization chamber output voltage.

Abstract: A gate driver circuit to receive an input drive signal and output an output drive signal is provided. The gate driver circuit may include a first capacitor having first and second terminals, a second capacitor having first and second terminals, a first set of switches to selectively couple the first terminals of the first and second capacitors to the input drive signal and a power supply voltage, a second set of switches to selectively couple the second terminals of the first and second capacitors to a reference voltage and a high impedance node, and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high impedance node. The comparator may output the output drive signal based on a comparison of the reference voltage and a voltage at the high impedance node.

Abstract: In some implementations, a controller may identify a block of a memory device that is scheduled for an erase operation. The controller may determine, using a machine learning model or a data structure, whether a wordline of the block is susceptible to a deeper erase condition before the erase operation. The data structure identifies wordlines that are susceptible to deeper erase conditions. The controller may perform a programming operation, on the wordline, to program a predetermined bit pattern on the wordline based on the wordline being susceptible to the deeper erase condition. The controller may perform the erase operation on the block after performing the programming operation.

Abstract: A metal-oxide semiconductor field-effect transistor (MOSFET) including a volume of semiconductor material, a split gate, a gate oxide, and a doped material in the volume of semiconductor material. The volume of semiconductor material presents laterally spaced first and second sides and a trench spaced between the sides. The split gate presents laterally spaced apart first and second gate sections. The trench is located between the first and second gate sections. The gate oxide underlies the first and second gate sections and at least partially fills the trench. The doped material is in contact with the gate oxide.

Abstract: An ideal diode bridge controller is provided that includes gate drivers to connect to transistors of a bridge rectifier in which the transistors are arranged as high-side transistors and low-side transistors. The gate drivers alternately switch the transistors to cause the bridge rectifier to convert an input voltage of either of two polarities to an output voltage of one of the two polarities. The gate drivers include low-side gate drivers for the low-side transistors, and respective ones of the low-side gate drivers include linear drive circuitry and digital drive circuitry. The linear drive circuitry drives a respective low-side transistor to switch on and off based on forward current through the respective low-side transistor. The digital drive circuitry detects a reverse current through the respective low-side transistor, and causes the respective low-side transistor to switch off in response to the reverse current.

Abstract: A system and method for a polymer with a low dielectric constant applied in targeted areas of a semiconductor using additive manufacturing and a second polymer having high thermal conductivity encasing the entire semiconductor are disclosed. The method may include applying, using an additive manufacturing technique, a first polymer to a first area of a semiconductor die. The first polymer may include a first filler having a dielectric constant of 3.3 or less. The method may also include applying a second polymer over the first polymer and encapsulating the semiconductor die. The second polymer may be different from the first polymer.

Abstract: One or more examples relate to an apparatus to switch data based on a bus identifier and a device identifier. Such an apparatus may include an upstream port for a respective peripheral component interconnect express (PCIe)-compliant communicative connection with a host; a downstream port for a respective PCIe-compliant communicative connection with an endpoint; and a switching logic. The switching logic may store a bus identifier and a device identifier for the endpoint; and switch data at least partially responsive to the bus identifier and the device identifier of the endpoint.

Abstract: An integrated circuit apparatus includes a transistor and a varactor. The transistor includes a transistor source and a transistor drain formed in a transistor well area of a semiconductor substrate, a transistor gate oxide formed over the substrate, and a transistor gate formed over the transistor gate oxide. The varactor is located laterally offset from the transistor and includes a pair of varactor source/drain regions formed in a varactor well area of the semiconductor substrate, a varactor gate insulator formed over the substrate, and a varactor gate formed over the varactor gate insulator, wherein the varactor gate is formed from a different material than the transistor gate.

Abstract: A vertical power metal oxide semiconductor field effect transistor includes a volume of semiconductor material, a channel, a source, a drain, and a gate. The volume of semiconductor material presents opposite vertically spaced first and second ends and an outer side perimeter adjacent the first end. The channel extends through the volume of semiconductor material from the first source to the drain. The source is located adjacent the first end. The gate at least substantially surrounds the outer perimeter of the volume of semiconductor material.

Abstract: A lateral junction field-effect transistor including a volume of semiconductor material including a first end, a second end spaced vertically from the first end, a first side, and a second side spaced laterally from the first side. A source and a drain are located at the first end of the volume of semiconductor material. Laterally spaced apart first and second gates are also located at the first end of the volume of semiconductor material. The source is positioned between the first and second gates.

Abstract: A system and method for a drift reset circuit for updating the input offset voltage in an ionization smoke detector are disclosed. The method may include monitoring an ionization chamber of a smoke detector for an alert. The method may also include periodically powering on a drift reset circuit to update an input offset voltage of an operational amplifier. The method may additionally include outputting the input offset voltage to the operational amplifier. The method may further include powering off the drift reset circuit.

Abstract: A junction field-effect transistor that is normally off rather than normally on, and a method of making such a device. The junction field-effect transistor includes a volume of semiconductor material, a first gate located at a first side of the semiconductor material, a second gate located at a second side opposite and spaced apart from the first gate, a Schottky barrier diode, and a drain. The Schottky barrier diode is located at a first end of the semiconductor material between the first and second gates, and replaces a conventional source. The drain is located at the second end, opposite the diode, and a region of the semiconductor material between the diode and the drain provides a channel. The Schottky barrier diode conducts in a forward mode (i.e., the device is on) only when the anode-to-cathode voltage exceeds the metal-to-semiconductor barrier potential, which means the device is normally off.