Abstract: A trench metal-oxide field-effect transistor (MOSFET) comprises a volume of semiconductor material, a drain, a trench, a source, a gate, and a gate oxide. The volume presents first and second sides and first and second ends. The trench is positioned in the volume. The trench has a trench bottom and opposite first and second laterally spaced trench sides. The source is located adjacent the first trench side. The gate is disposed within the trench and includes a first side surface, a spaced apart second side surface, and a bottom surface positioned at a lower edge therebetween. The gate oxide is positioned between the gate and the trench and includes a first section formed from a first material having a first dielectric constant and a second section formed from a second material having a second dielectric constant, with the first dielectric constant being less than the second dielectric constant.

Abstract: In some implementations, a controller may select a physical block, of a user data virtual block (VB), for a host write operation or a garbage collection operation. The user physical block previously stored user data. The user physical block has previously been programmed in accordance with triple-level cell (TLC) programming. The controller may determine that an average bit error rate (BER) of the user physical block exceeds an average BER of the VB. The controller may, based on determining that the average BER of the physical block exceeds the average BER of the user VB: swap, for the VB, the user physical block with a system physical block that is allocated for storing system data; swap, for the VB, the user physical block with a reserved physical block; or cause a program time, of the user physical block, to be increased.

Abstract: A method may include generating a status signal, the status signal to indicate a status of Error-Locator-Polynomial (ELP) determination by an ELP determination circuit; and controlling the ELP determination by the ELP determination circuit at least partially responsive to a value of the status signal.

Abstract: An apparatus includes a body having walls defining a cavity therebetween, the cavity containing an amount of a subject material therein. A channel structure including a channel substrate with channels having a substantially uniform width formed therein is disposed along a portion of the walls of the body, and a liner material is disposed over portions of internal surfaces of the channels.

Abstract: An integrated circuit component includes voltage reference circuitry. The voltage reference circuitry is tuned to be relatively insensitive to temperature changes. However, due to process variations, the bandgap voltage reference circuitry in the voltage reference circuitry may have a larger output variation and larger output voltage temperature dependence than desired. In order to reduce the dependence, programmable trim circuitry can redirect some of the current passing through the transistors of the bandgap voltage reference circuitry, trimming the bandgap voltage reference circuitry to have reduced output voltage variation and reduced temperature dependence.

Abstract: Junction field-effect transistors (JFETs) with separated source and gate regions, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a source region, a drain region, a drift region, and multiple gate regions. The source region is within a mesa and has a first conductivity type. The drain region is below the source region and also has the first conductivity type. The drift region extends vertically between the source region and the drain region, and the drift region also has the first conductivity type, but the drift region has a lower doping concentration than the source region and the drain region. The gate regions are below trenches on opposite sides of the mesa, separated from the source region, and the gate regions have a second conductivity type different than the first conductivity type.

Abstract: An apparatus comprising a substrate; a Schottky barrier diode comprising a metal layer and a mesa structure, the mesa structure comprising a first portion of the substrate, wherein the first portion of the substrate extends vertically from a second portion of the substrate; and a planar metal-oxide-semiconductor field-effect transistor (MOSFET) comprising at least a portion of the second portion of the substrate, wherein the planar MOSFET is coupled in parallel with the Schottky barrier diode.

Abstract: A trench metal oxide semiconductor field-effect transistor includes a thicker bottom gate oxide. A volume of semiconductor material includes first and second ends. A source is located at a first end, and a drain is provided. A trench extends into the volume semiconductor material from the first end thereof. The trench is adjacent to the source and includes a trench bottom, a trench side extending between the trench bottom and the first end of the volume of semiconductor material, and trench a width. A gate oxide is located within the trench. The gate oxide includes a bottom layer that is adjacent the trench bottom and presents a bottom oxide layer average thickness, and a side layer that extends along the trench side and presents a side oxide layer average thickness. The bottom oxide layer average thickness is greater than the side oxide layer average thickness.

Abstract: A metal-oxide semiconductor field-effect transistor (MOSFET) includes a volume of semiconductor material, a gate, and a shielding region. The volume of semiconductor material includes a top, an opposite bottom spaced vertically from the top, a first side, and a laterally opposite second side spaced from the first side. The volume of semiconductor material forms a trench extending from the top and spaced between the sides. The trench includes opposite first and second trench sides. The gate is located within the trench. The shielding region is located below at least a portion of the gate and extends laterally beyond the second trench side toward the second side of the volume of semiconductor material.

Abstract: A system comprises a host system and a data storage system. The data storage system includes a controller including at least one processor and computer readable media including volatile and non-volatile memory components. The computer readable media stores instructions that, when executed by the at least one processor, cause the at least one processor to: receive a prefetch data request from the host system, the prefetch data request including a physical block address (PBA) for a data segment; responsive to receiving the data request, retrieve the data segment from the non-volatile memory component by locating the data segment in the non-volatile memory using the PBA received from the host; and store the data segment in the volatile memory component.

Abstract: A semiconductor device package comprising a frame comprising a conductive material, the frame comprising a plurality of connectors; a die attached to the frame, the die comprising a semiconductor device; a first dielectric material in contact with at least a portion of a top surface of the die and a portion of the frame; and a second dielectric material encapsulating the first dielectric material.

Abstract: A data storage system includes a memory device and a controller. The memory device includes a set of planes and a wordline including a set of pages. The controller includes a first and second minimum write cache control buffer (mWCCBs), processor(s), and a memory. The memory includes instructions, that when executed the processor(s), cause the processor(s) to: determine that an amount of outstanding data of a data stream is not sufficient to occupy the set of planes; store a first portion of the outstanding data in the first mWCCB; release the first portion to the memory device; in coordination with the release of the first portion of the outstanding data, store a second portion of the outstanding data in the second mWCCB; release the second portion to the memory device; and write the first and second portions of the outstanding data to a subset of the set of pages.

Abstract: A trench metal oxide semiconductor field-effect transistor includes an epitaxially grown rather than implanted doped channel region. A method of making same is also disclosed. A second volume of doped semiconductor material is epitaxially grown above a first volume of semiconductor material, with the first and second volumes of semiconductor material having opposite polarities. A source material is implanted into an upper region of the second volume of semiconductor material, leaving a lower region of the second volume of semiconductor material for a well. A trench is etched adjacent to the source material for a gate, and a channel extends through the well and alongside the trench. Epitaxially growing rather than implanting the second volume of semiconductor material results in a less Gaussian, or less normal, distribution of dopants and a more uniform distribution of dopants across the well through which the channel extends.

Abstract: A junction field-effect transistor (JFET) may include a volume of semiconductor material that presents a top, an opposite bottom, a first side, and an opposite second side. The JFET may include laterally spaced first and second gates. A source may be positioned adjacent the top of the volume of semiconductor material, with the source being at least in part laterally between the first and second gates. A drain may be spaced apart from the source, with a channel being defined therebetween. The first gate may include a lateral gate portion extending laterally to underlie the source and at least a portion of the second gate, the lateral gate portion causing the channel to include a lateral channel portion defined between the lateral gate portion and the second gate.

Abstract: An apparatus, such as a Controller Area Network (CAN)-based node, may include memory storing a plurality of lookup tables. The apparatus may also include processing circuitry to calculate calibrated brightness values for light emitting diodes (LEDs), where each calibrated brightness value is based on a value indicating a desired brightness, a temperature value, and an age value. The calibrated brightness values may be stored in the lookup tables and output brightness signals for LEDs of an array may be determined using the stored lookup tables.

Abstract: Accumulators for reducing frequency of samples and related apparatuses, systems, and methods are disclosed. An apparatus includes a first accumulator and a second accumulator. The first accumulator provides a first total. The first total corresponds to a sum of a current sample value of an input signal and a previous value of the first total. The second accumulator provides a second total. The second total corresponds to a sum of the first total and a previous value of the second total.

Abstract: A data storage device with directional traffic management that includes a non-volatile memory media configured to store data and a controller. The controller includes a dedicated read interface, a dedicated write interface, non-transitory computer readable media and at least one processor. When executed by at least one processor, the instructions cause the at least one processor to receive from a host a read request at the dedicated read interface and fulfill the read request using the dedicated read interface to retrieve corresponding requested data from the non-volatile memory media and send the requested data to the host, and receive from the host a write request at the dedicated write interface for corresponding provided data and fulfill the write request using the dedicated write interface to send the provided data to the non-volatile memory media.

Abstract: A system and method for a mobile microscope is disclosed. The system includes a platform to move about an environment; a sampler tool coupled to the platform; a microscope coupled to the platform; a camera coupled to the microscope; and a control circuit to: instruct the platform to move about an environment; instruct the sampler tool to obtain a sample and place the sample in a view field of the microscope; instruct the camera to capture an image of the sample, the image enlarged by the microscope; receive the image from the camera; analyze, using a neural network, the image to classify the sample; and output a classification of the sample.

Abstract: A semiconductor device comprising a substrate having a first type dopant; an active region; a termination region laterally adjacent to the active region, the termination region comprising a plurality of doped channels in the substrate, the plurality of doped channels having a second type dopant; and a trench in the substrate, wherein the trench is laterally between two of the plurality of doped channels, wherein the trench is filled with a dielectric material; and a dielectric layer on the plurality of doped channels and the trench.

Abstract: A system comprising a scan chain comprising a plurality of scan channels coupled to combinational logic, wherein a scan channel comprises a plurality of memory elements arranged in series, wherein an input to the scan channel is to be serially shifted through the plurality of memory elements of the scan channel; and circuitry to, based on a value of a control signal couple inputs of a first subset of the plurality of scan channels to a scan input signal, the scan input signal to communicate a test pattern; and couple inputs of a second subset of the plurality of scan channels to outputs of other scan channels of the plurality of scan channels.