Abstract: A semiconductor device comprising a substrate having a first type dopant; an active region; a termination region laterally adjacent to the active region, the termination region comprising a plurality of doped channels in the substrate, the plurality of doped channels having a second type dopant; and a trench in the substrate, wherein the trench is laterally between two of the plurality of doped channels, wherein the trench is filled with a dielectric material; and a dielectric layer on the plurality of doped channels and the trench.

Abstract: A system comprising a scan chain comprising a plurality of scan channels coupled to combinational logic, wherein a scan channel comprises a plurality of memory elements arranged in series, wherein an input to the scan channel is to be serially shifted through the plurality of memory elements of the scan channel; and circuitry to, based on a value of a control signal couple inputs of a first subset of the plurality of scan channels to a scan input signal, the scan input signal to communicate a test pattern; and couple inputs of a second subset of the plurality of scan channels to outputs of other scan channels of the plurality of scan channels.

Abstract: A junction field effect transistor (JFET) includes a volume of semiconductor material, a source, and first and second gate contacts. The volume of semiconductor material includes a top, an opposite bottom spaced vertically from the top, a first side, a laterally opposite second side spaced from the first side, a first doped region, a second doped region, a drift region, and first and second trenches respectively along the first and second sides. The source is positioned along the top. The first and second gate contacts are respectively positioned in the first and second trenches. The drift region extends between the first and second doped regions. The first and second doped regions respectively define first and second junctions with the drift region including first and second topmost portions. The first and second gate contacts are vertically nearer to the top than the topmost portions of the first and second junctions.

Abstract: An electrical component package includes an electrical component, a frame, and a cavity in the frame, with the electrical component being at least in part aligned with the cavity.

Abstract: Storage controllers with remote management functionality, and devices and systems incorporating the same, are disclosed herein. In one example, a storage controller card includes a storage controller and a remote management controller. The storage controller manages access to a plurality of storage devices, and the remote management controller manages access to the storage controller over a network and independently of a host processor.

Abstract: A semiconductor device comprising a substrate having a first type dopant; an active region; at least one doped channel in the substrate outside of the active region, the at least one doped channel having a second type dopant; at least one trench formed in the substrate lateral to the at least one doped channel and outside of the active region, wherein the at least one trench is filled with an oxide; and a dielectric layer on the at least one trench.

Abstract: An integrated circuit device includes a first conductive contact to be conductively coupled to a first memory component and a second memory component of a plurality of memory components in a computing system, a second conductive contact to be conductively coupled to a first processing unit in the computing system, a memory controller circuit, and an embedded processor. The memory controller circuit is to cause first executable instructions received from the first processing unit to be stored in the first memory component and to cause the computing system to transition from a first power state to a second power state. During the second power state the second memory component and the first processing unit are to be powered down and the first memory component is to be powered up. The embedded processor is to execute the first executable instructions stored in the first memory component.

Abstract: A data storage system comprises at least one processor and computer-readable media including a non-volatile memory component. The computer-readable media stores instructions that, when executed by the at least one processor, cause the at least one processor to: monitor operating conditions associated with the data storage system; and throttle performance of the data storage system based at least in part on the monitored operating conditions, the throttling performance including one or more of: adjusting a frequency of a clock signal, relocating critical data within the non-volatile memory component, or adjusting one or more parameters of the non-volatile memory component.

Abstract: A Schottky barrier diode (SBD) comprises a volume of semiconductor material presenting opposite first and second ends, a metal layer contacting the first end to define a Schottky contact, and a plurality of doped material pockets dispersed in the volume of semiconductor material adjacent the first end. Each of the doped material pockets extend from the first end to define a cross-sectional shape relative to the direction of extension. The cross-sectional shape of each of the doped material pockets presents a body and a projection extending laterally from the body.

Abstract: An apparatus including a planar metal oxide semiconductor field-effect transistor and a trench Schottky barrier diode that are physically and functionally integrated into a single, continuous structure, and a method of making such an apparatus. The integrated, trench Schottky barrier diode is located over a junction field-effect transistor neck region which is adjacent to the planar metal oxide semiconductor field-effect transistor. The Schottky barrier diode and the planar metal oxide semiconductor field-effect transistor may be located in a single, continuous volume of semiconductor material. The planar metal oxide semiconductor field-effect transistor may include first and second transistor sides spaced on opposite sides of the junction field-effect transistor neck region, such that the trench Schottky barrier diode may be located between the first and second transistor sides.

Abstract: One or more examples relate to a method that includes: applying oversampling to data on a reception datapath of a physical layer; generating a first signal indicating relationships between patterns exhibited by portions of oversampled data and a predetermined pattern; generating a second signal indicating an observed feature of the first signal, the observed feature indicative of a highest relationship between the patterns exhibited by respective portions of oversampled data and the predetermined pattern; and providing the second signal to indicate presence of a portion of data corresponding to the predetermined pattern at a coupled portion of the reception datapath of the physical layer.

Abstract: A semiconductor device comprising: a volume of semiconductor material including an opposite bottom spaced from the top, a first side, and an opposite second side spaced from the first side; a source positioned along the top; a drift region having a first charge carrier polarity; a well having a second charge carrier polarity that is opposite the first charge carrier polarity and forming a well junction with the drift region; and a second region adjacent the well and forming a second region junction with the drift region. The second region junction is nearer the bottom and nearer the second side of the volume of semiconductor material than the well junction.

Abstract: A system, method, and apparatus providing current sensing capabilities for semiconductor devices. A method comprises sensing, through a first external connector of at least one semiconductor device package, a voltage on a first current path including a first semiconductor device of the at least one semiconductor device package; sensing, through a second external connector of the at least one semiconductor device package, a voltage on a second current path including a second semiconductor device of the at least one semiconductor device package; and detecting that a magnitude of current through the first current path is different from a magnitude of current through the second current path based on the voltage on the first current path and the voltage on the second current path.

Abstract: A computer-implemented method, media, and systems for setting a deallocate value for a flag within a data storage device may include: receiving, by the data storage device, a command from a host; dividing, based on the command, a range of logical block addresses corresponding to the data storage device into cache-aligned sub-ranges; determining that the sub-ranges include a full cache line; and setting, based on the command and the determination that the sub-ranges include the full cache line, the deallocate value for the flag in the full cache line.

Abstract: A semiconductor device includes a source electrode. The source electrode includes spaced apart first and second metal layers and a via extending between and electrically connecting the first metal layer and the second metal layer. The metal layer includes first and second source electrode contacts. The source second metal layer includes a monolithic source pad spaced apart from and electrically connected to the first and second source electrodes.

Abstract: A power module comprises a plurality of dies including a first die subset and a second die subset, with each subset including one or more of the dies. The second die subset is associated with a power module hotspot and has a higher operating temperature than the first die subset. A first encapsulation material is disposed on the first die subset. A second encapsulation material is disposed on the second die subset. The second encapsulation material has higher thermal conductivity than the first encapsulation material.

Abstract: A semiconductor device comprising a volume of semiconductor material including a first end, a second end spaced vertically from the first end, a first side, and a second side spaced laterally from the first side; a first integrated planar MOSFET located at the first side of the volume of semiconductor material; a second integrated planar MOSFET located at the second side of the volume of semiconductor material; and a trench located at the first end of the volume of semiconductor material between the first and second integrated planar MOSFETs. An integrated trench Schottky barrier diode comprising a Schottky metal is located within the trench. Methods for making the semiconductor device are also disclosed.

Abstract: A trench power semiconductor device comprising a silicon carbide drain layer, a silicon carbide drift layer over the silicon carbide drain layer and a first silicon layer over the silicon carbide drift layer. A second silicon layer over the first silicon layer with a source silicon carbide layer over the second silicon layer. A trench formed through the source silicon carbide layer, through the second silicon layer and into at least partially the first silicon layer. A gate terminal contact formed on the trench with a drain terminal contact formed on the silicon carbide drain layer.

Abstract: One or more examples relate to an apparatus that includes an error detector, an oscillator, an analog proportional path, and a digital integral path. The oscillator includes an analog proportional input, a digital integral input, and an analog integral input. The analog proportional path provides a control signal for the analog proportional input of the oscillator. The digital integral path provides a control for the digital integral input and the analog integral input of the oscillator. A first signal path of an interface includes a direct coupling between the digital phase detector and integrator and the digital integral input of the oscillator. A second signal path of the interface includes a digital-to-analog converter (DAC) with a filtered delta-sigma modulator (DSM) input between the digital phase detector and integrator and the analog integral input of the oscillator.

Abstract: EEPPROM array having memory cells arranged in rows and columns, wherein the memory cells have a select transistor and a sense transistor; memory sections include a plurality of memory cells and a section select transistor; a source line physically coupled to a source terminal of a section select transistor; a wordline physically coupled to a gate of a section select transistor and a gate of a select transistor; and a sense gate line physically coupled to a gate of a sense transistor. An erase operation may be done by applying: a low voltage to the source line; a high voltage to the sense gate line; and a middle voltage to the wordline.