Abstract: Methods and systems are provided for associating respective ones of a plurality of beacons with respective ones of a plurality of products; receiving a product specification from a user; identifying a product of the plurality of products corresponding to the product specification; and notifying the user of the location of a respective beacon of the plurality of beacons associated with the identified product.

Abstract: A device for measuring phase noise, including a sampler to sample an input signal, an input filter to receive an input from the sampler, a noise generator to generate a noise signal, a combiner to receive input from, respectively, the input filter and the noise generator, the combiner to output an integrated noise output measurement. The input filter may operate in either the time domain or the frequency domain. The noise generate may generate a noise signal based on the sampler output, or may generate a noise estimate value based on the sampler output.

Abstract: A system and method is provided including a first pulse width modulation (PWM) generator circuit including a first timer to generate a first cycle count, a first configuration register to define characteristics of a first electrical pulse to be generated, and a trigger cycle count specifying a timing of a first trigger signal, and a first load enable input to load a new configuration value into the first configuration register, a second PWM generator circuit including a second timer to generate a second cycle count, a second configuration register to define characteristics of a second electrical pulse to be generated, a second load enable input to load a new configuration value into the second configuration register, and a load enable selector to selectively drive the second load enable input based on the first trigger signal.

Abstract: An apparatus for power management of a static random access memory (SRAM) bank is provided. The apparatus may include a memory core to store data, a memory peripheral connected to the memory core for supporting memory operations, a core power pin connected to a power source to supply power to the memory core, a peripheral power pin connected to the power source via a power switch, the power switch to selectively gate power to the memory peripheral, an isolation cell connected to one or more data pins of the SRAM bank, the isolation cell to isolate the data pins when the memory peripheral is powered down, and power management circuitry to monitor access patterns of the SRAM bank, determine how frequently the SRAM bank is accessed, and place the SRAM bank in deep retention mode by controlling the power switch and the isolation cell.

Abstract: A system and method for an electrostatic discharge (ESD) clamp circuit containing a disable circuit to selectively disable a discharge circuit is disclosed. An electrostatic discharge (ESD) clamp circuit including a discharge circuit to discharge a current flow during a transient ESD voltage event; a disable input to receive a disable input signal; and a disable circuit to, based upon the disable input signal, selectively disable the discharge circuit. When the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled; and when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit.

Abstract: A device with one-time-programmable (OTP) memory, boot code, volatile memory, and non-volatile memory. Boot code may use information in OTP to authenticate code of an implicit owner of the electronic device; receive a first create owner container request; create a first owner container comprising a first signed data image; store the first owner container; and use the first signed data image to authenticate first executable code associated with the first owner. Boot code may transfer ownership from the first owner to a second owner, including authenticating a signed transfer of ownership command using a key stored in the first owner container and creating a second owner container comprising a second signed data image associated with the second owner; storing the second owner container; revoking the first owner container; and using the second signed data image to authenticate second executable code associated with the second owner of the electronic device.

Abstract: One or more examples relate to a method. The method includes: receiving up/down error signals indicative of duty cycle mismatch between a reference clock signal and a changed feedback clock signal that represents an output clock signal generated by a clock tracking circuit to track the reference clock signal; setting a duty cycle of a changed feedback clock signal to reduce duty cycle mismatch indicated by the up/down error signals; and providing the changed feedback clock having set duty cycle.

Abstract: A system and method for a mobile microscope is disclosed. The system includes a platform to move about an environment; a sampler tool coupled to the platform; a microscope coupled to the platform; a camera coupled to the microscope; and a control circuit to: instruct the platform to move about an environment; instruct the sampler tool to obtain a sample and place the sample in a view field of the microscope; instruct the camera to capture an image of the sample, the image enlarged by the microscope; receive the image from the camera; analyze, using a neural network, the image to classify the sample; and output a classification of the sample.

Abstract: A circuit to suppress ringing in a Controller Area Network (CAN) bus having a CAN high (CANH) wire and a CAN low (CANL) wire is provided. The circuit may include processing circuitry to generate a CAN control signal, and a transconductance amplifier to receive a first input signal corresponding to the CAN control signal and a voltage signal from the CANL wire, and to generate an output current signal based on a difference between the first input signal and the voltage signal from the CANL wire. An output terminal of the transconductance amplifier may be coupled to the CANH wire to source current to or sink current from the CANH wire.

Abstract: A power semiconductor device is provided that includes paralleled transistor cells, and a common source, a common drain and a common gate operatively coupled to the paralleled transistor cells. The power semiconductor device also includes a plurality of common gate contact pads operatively coupled to the common gate, and one or more resistors coupled to respective one or more common gate contact pads of the plurality of common gate contact pads. The one or more resistors are also coupled between the respective one or more common gate contact pads and the common gate. The plurality of common gate contact pads provide a selectable resistive decoupling of the common gate by connection of one of the plurality of common gate contact pads.

Abstract: An apparatus comprises a data width converter and a forward error correction (FEC) encoder. The data width converter includes an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width. The FEC encoder includes an input to receive the second output data stream at the second output bit width. The FEC encoder includes an output to produce parity bits at least partially based on multiple received symbols of the second output data stream having the second output bit width. The parity bits for insertion in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a transmit data path, and the FEC encoder is in parallel with the transmit data path.

Abstract: One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.

Abstract: A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.

Abstract: Ovens for atomic clocks may include a body including a cavity within the body. A plurality of heating elements may be distributed around the body, each heating element of the plurality including coils of electrically resistive material. An arrangement of the plurality of heating elements may be such that far fields of magnetic fields having opposite polarities induced by respective coils of the heating elements overlap.

Abstract: A controller and a method is provided for controlling a capacitance of an LC circuit having a circuit frequency including, a variable capacitor to couple with an external inductor as part of an LC circuit, a target value, a spread spectrum function to generate an adjustment value, and a circuit to poll the target value, call the spread spectrum function, and set a capacitance of the variable capacitor based on the sum of the target value and the adjustment value.

Abstract: A manufactured product may include a machine-readable physical identifier and the machine-readable physical identifier may be stored in a tracking file. The machine-readable physical identifier may be encoded with manufacturing information related to the manufactured product, including but not limited to manufacturing location, lot number and manufacturing date. The tracking file may be updated based on one or more supply chain operations, including but not limited to a testing operation, a shipping operation or a delivery operation. The tracking file may include information on testing results, shipping origin and destinations and delivery locations. The tracking file may be delivered to a customer along with the manufactured products listed in the tracking file.

Abstract: A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the fin-shaped portion of the drift layer. An insulating layer over the doped-well layer and over the recessed portion of the drift layer. A gate electrode over the insulating layer.

Abstract: Methods based on polyhedron models using computational operations for distributing data and parities among different data storage media. Devices, systems, and methods that split data into data strips, wherein the number of data strips equals the number of vertices of a polyhedron and respective ones of the number of the data strips correspond to respective ones of the number of vertices of the polyhedron; construct a number of parities, wherein the number of parities equals the number of faces of the polyhedron and respective ones of the number of parities correspond to respective ones of the number of parities of the polyhedron, wherein respective ones of the number of parities are constructed by computationally operating the data strips corresponding to vertices respectively associated with a face of the polyhedron corresponding to the respective parity; and distribute subsets of data strips and subsets of parities to subsets of storage media.

Abstract: An apparatus comprising: a support structure; and a first electrically-conductive material arranged at the support structure to define a first continuous path for first electrical current to flow between a first location and a second location, the first continuous path comprising: a first path portion defining a first generally-clockwise path for the first electrical current to flow around a first axis, the first path portion including a first inner-circumferential portion and a first outer-circumferential portion, the first inner-circumferential portion located closer to a central axis than the first outer-circumferential portion, a radius of curvature of the first inner-circumferential portion being greater than a radius of curvature of the first outer-circumferential portion; and a second path portion defining a first generally-counter-clockwise path for the first electrical current to flow around a second axis, the first path portion and the second path portion circumferentially arranged around the centra

Abstract: Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface. Also disclosed is a PHY transceiver of a 10SPE PHY, where the transceiver includes a circuitry for controlling a starting polarity of frames.