Abstract: One or more examples relate to an apparatus to switch data based on a bus identifier and a device identifier. Such an apparatus may include an upstream port for a respective peripheral component interconnect express (PCIe)-compliant communicative connection with a host; a downstream port for a respective PCIe-compliant communicative connection with an endpoint; and a switching logic. The switching logic may store a bus identifier and a device identifier for the endpoint; and switch data at least partially responsive to the bus identifier and the device identifier of the endpoint.

Abstract: An integrated circuit apparatus includes a transistor and a varactor. The transistor includes a transistor source and a transistor drain formed in a transistor well area of a semiconductor substrate, a transistor gate oxide formed over the substrate, and a transistor gate formed over the transistor gate oxide. The varactor is located laterally offset from the transistor and includes a pair of varactor source/drain regions formed in a varactor well area of the semiconductor substrate, a varactor gate insulator formed over the substrate, and a varactor gate formed over the varactor gate insulator, wherein the varactor gate is formed from a different material than the transistor gate.

Abstract: A vertical power metal oxide semiconductor field effect transistor includes a volume of semiconductor material, a channel, a source, a drain, and a gate. The volume of semiconductor material presents opposite vertically spaced first and second ends and an outer side perimeter adjacent the first end. The channel extends through the volume of semiconductor material from the first source to the drain. The source is located adjacent the first end. The gate at least substantially surrounds the outer perimeter of the volume of semiconductor material.

Abstract: A lateral junction field-effect transistor including a volume of semiconductor material including a first end, a second end spaced vertically from the first end, a first side, and a second side spaced laterally from the first side. A source and a drain are located at the first end of the volume of semiconductor material. Laterally spaced apart first and second gates are also located at the first end of the volume of semiconductor material. The source is positioned between the first and second gates.

Abstract: A system and method for a drift reset circuit for updating the input offset voltage in an ionization smoke detector are disclosed. The method may include monitoring an ionization chamber of a smoke detector for an alert. The method may also include periodically powering on a drift reset circuit to update an input offset voltage of an operational amplifier. The method may additionally include outputting the input offset voltage to the operational amplifier. The method may further include powering off the drift reset circuit.

Abstract: A junction field-effect transistor that is normally off rather than normally on, and a method of making such a device. The junction field-effect transistor includes a volume of semiconductor material, a first gate located at a first side of the semiconductor material, a second gate located at a second side opposite and spaced apart from the first gate, a Schottky barrier diode, and a drain. The Schottky barrier diode is located at a first end of the semiconductor material between the first and second gates, and replaces a conventional source. The drain is located at the second end, opposite the diode, and a region of the semiconductor material between the diode and the drain provides a channel. The Schottky barrier diode conducts in a forward mode (i.e., the device is on) only when the anode-to-cathode voltage exceeds the metal-to-semiconductor barrier potential, which means the device is normally off.

Abstract: An apparatus may have a light fixture including a housing and a light element located within the housing. The apparatus may also include a face plate coupled to the light fixture. The apparatus may further include a detector. The detector may be coupled to the housing at a location behind a back surface of the face plate.

Abstract: A data storage system includes a memory device (e.g., a solid state drive) including a wordline (WL), a memory (e.g., a random access memory) including instructions stored thereon, and at least one processor. The memory includes instructions stored thereon that, when executed by the at least one processor, cause the at least one processor to: select a machine learning (ML) model based at least in part on error values for the WL; determine, by the ML model, a read voltage threshold; and read data from the WL using the read voltage threshold.

Abstract: A data storage system includes a memory device (e.g., a solid state drive), a memory (e.g., a random access memory) including instructions stored thereon, and at least one processor. The memory device includes a block and a plurality of wordlines (WLs). The memory includes instructions stored thereon that, when executed by the at least one processor, cause the at least one processor to: detect errors associated with the block; determine, based at least in part on the detected errors, a cross-temperature condition; adjust a pass through voltage (Vpassr) based on the determined cross-temperature condition; and perform a read operation at least in part by: applying a read voltage to a first WL of the plurality of WLs; and applying the adjusted Vpassr to one or more remaining WLs of the plurality of WLs.

Abstract: An integrated circuit (IC) package includes a bare die mounted on a substrate, and a conductive routing region including conductive routing structure and an inductor. The conductive routing structure is conductively connected to the bare die, and includes conductive elements formed in multiple conductive routing layers in the conductive routing region. The inductive device includes a winding formed in at least one conductive routing layer of the multiple conductive routing layers.

Abstract: A system and method for compensating for offset voltage drift using a static trim based on measurements at two temperatures are disclosed. The method may include reading a first temperature and a second temperature from a temperature sensor, measuring a first untrimmed offset voltage at the first temperature, and measuring a second untrimmed offset voltage at the second temperature. The method may include calculating an offset voltage drift based on a difference between the first and second untrimmed offset voltages and a difference between the first and second temperatures, calculating an offset voltage drift trim using the offset voltage drift, and storing the offset voltage drift trim for application by a first digital-to-analog converter. The method may include calculating an offset voltage trim at the second temperature, using the offset voltage drift trim at the second temperature, and storing the offset voltage trim for application by a second digital-to-analog converter.

Abstract: A system and method for a high temperature strain gauge are disclosed. The system may include a mechanical component. The system may also include a strain gauge to measure a strain of the mechanical component. The strain gauge may include a first end of a first support leg mounted on the mechanical component. The strain gauge may also include a first end of a second support leg mounted on the mechanical component opposite the first support leg. The second support leg may be symmetric to the first support leg and have a size substantially similar as the first support leg. The strain gauge may also include a strain sensor between a second end of the first support leg and a second end of the second support leg.

Abstract: A computer-implemented method for increasing reliability of a current operation performed by a NAND flash device, the method comprising performing, via a flash controller, the steps of determining a temperature of the NAND flash device, determining that the temperature satisfies a threshold, and responsive to the determination that the threshold is satisfied, performing additional operations on the NAND flash device.

Abstract: There are systems and methods for automatic mold detection, disinfection, and historical documentation. A system comprises: a drone; a data collection module to collect mold diagnostic data from an interior of a structure and configured to be transported by the drone; a disinfectant module to remediate a mold condition and configured to be transported by the drone; a mold diagnostic circuit configured to: diagnose mold conditions based on the mold diagnostic data; instruct the disinfectant module to remediate a portion of the interior structure based on diagnosed mold conditions; and maintain a historic record of mold conditions and remediations.

Abstract: A computer-implemented method for reducing errors in a NAND flash device, the method comprising: determining an open block state of a block of NAND flash included in the NAND flash device, the block of NAND flash including a plurality of wordlines (WLs) including a selected WL and an unselected WL; responsive to determining that the block of NAND flash is in an open state, determining an adjusted pass-through voltage (Vpassr); and performing a read operation on the selected WL by applying the adjusted Vpassr to the unselected WL.

Abstract: A multi-channel ADC system may include a plurality of input channels coupled to input signals. A multiplexer may couple one or more of the plurality of input channels to one or more multiplexer output channels. A control circuit may be coupled between the multiplexer output channels and an ADC. In operation, a configuration setting may configure the multi-channel ADC system in one of a plurality of configurations, including but not limited to single-ended, differential, pseudo-differential and hybrid configurations. The ADC may convert the plurality of input channels based on the configuration setting.

Abstract: An apparatus, system, and method for a die seal layout design to improve adhesion of a polyimide layer to a passivation layer in semiconductor packaging is disclosed. The apparatus may include an outer seal ring on a semiconductor die. The apparatus may also include an inner seal ring on a portion of the semiconductor die. The apparatus may further include a trench between the outer seal ring and the inner seal ring. The apparatus may include a passivation layer covering the semiconductor die including the outer seal ring and the inner seal ring. The apparatus may additionally include a polyimide layer covering a portion of the passivation layer over the inner seal ring and a portion of the trench.

Abstract: A system and method for debugging logic elements in a configurable logic block using only one pin. A synchronization pulse is generated, and each logic element is connected, in turn, using a digital selector switch. The synchronization pulse and a logic state of each logic element are received, in turn, by an output buffer. First, second, and third digital outputs levels are enabled on a single output line using a voltage divider configuration of resistors connected to the output line of the output buffer. The output levels include the synchronization pulse, a low logic state, and a high logic state. The synchronization pulse and the logic state of each logic element are outputted as the different output levels, in turn, via a single debug pin connected to an oscilloscope or other display device for visualization. The debug pin may be shared with other functions when not being used for debugging.

Abstract: A method of decommissioning a solid-state drive including a non-volatile memory media and a controller. Decommissioning is achieved by a disabling command sequences, internal communication channels, and interfaces. A non-volatile memory media is permanently disabled by short circuiting an internal high voltage generator to an electrical ground so that a high voltage cannot be generated for an operation required to access data on the memory media. The short circuit path may be enabled using a one-time programmable element. Further, an ability of a non-volatile memory media interface to initiate a command sequence that is required to access the memory media is disabled, and a status confirmation indicating that the memory media has been disabled is issued. A controller is also permanently disabled by disabling an ability of a flash interface to communicate with the non-volatile memory media so that no commands can be received by the memory media.

Abstract: An apparatus comprises a microelectromechanical system (MEMS) including a semiconductor body. The semiconductor body comprises a first resonator, a second resonator, a supporting portion, and one or more heating elements of a heater. The first resonator is to resonate at a first resonating frequency that is generally frequency-stable over a predetermined temperature range. The second resonator is to resonate at a second resonating frequency that is generally linearly decreasing or increasing as temperature increases over the predetermined temperature range. The supporting portion is to support both the first resonator and the second resonator. The one or more heating elements of the heater are on, or in, the supporting portion.