Abstract: A processor may access multiple templates related to an initial firmware version. The processor may identify a customized value within the first template. The processor may generate source code for a second firmware version based on the template. This source code includes indications of the customized value found in the first template, enabling the creation of an updated firmware version while retaining specific customizations from the original.

Abstract: Systems and methods track a user's line-of-sight relative to objects through a transparent LCD display to provide information about the objects to be displayed on the display proximate the line-of-sight between the object being viewed and the user's head to create an augmented reality environment for the user. A method comprising: determining a position of an object; determining a position of a transparent display; determining a line-of-sight extending between a user's eye and the object through the transparent display; determining where the line-of-sight intersects the transparent display; and displaying object information corresponding to the object via the transparent display proximate where the line-of-sight intersects the transparent display.

Abstract: A field effect transistor (FET) that is radiation-hardened against a single-event burnout effect comprises a volume of semiconductor material, a gate, a source, a drain, a drift region, and a doped drift region. The gate is positioned at a first end of the structure. The source is positioned at the first end of the structure. The drain is spaced apart from the source. The drift region is positioned between the source and the drain. The doped region includes a plurality of doped zones spaced apart from one another and positioned between the drain and the drift region. The doped drift region is configured to provide radiation hardening against a single event burnout.

Abstract: A semiconductor device comprises a volume of semiconductor material, an integrated metal oxide semiconductor field-effect transistor (MOSFET), and an integrated Schottky barrier diode (SBD). The volume of semiconductor material includes a first end, a second end spaced vertically below the first end, a first side, and a second side spaced laterally from the first side. The volume of semiconductor material includes an upward projection spaced from the first side. The MOSFET includes a first transistor side located adjacent the first side of the volume of semiconductor material. The first transistor side includes a first well and a first gate. The SBD comprises a Schottky material positioned over at least part of the upward projection.

Abstract: Some examples of the teachings herein include a system comprising: a silicon die including an inductor element; a crystal connected to the silicon die by bonding wires; and a non-conductive spacer between the silicon die and the crystal; wherein the non-conductive spacer has a thickness defining a distance between the silicon die and the crystal, the distance selected to reduce an effect of the crystal on a magnetic flux of the inductor.

Abstract: A method of decommissioning a solid-state drive including a non-volatile memory media and a controller. Decommissioning is achieved by a disabling command sequences, internal communication channels, and interfaces. A non-volatile memory media is permanently disabled by short circuiting an internal high voltage generator to an electrical ground so that a high voltage cannot be generated for an operation required to access data on the memory media. The short circuit path may be enabled using a one-time programmable element. Further, an ability of a non-volatile memory media interface to initiate a command sequence that is required to access the memory media is disabled, and a status confirmation indicating that the memory media has been disabled is issued. A controller is also permanently disabled by disabling an ability of a flash interface to communicate with the non-volatile memory media so that no commands can be received by the memory media.

Abstract: In one aspect, a method of adjusting a first oscillating signal, includes generating a relationship prediction responsive to a deep learning model configured to predict a relationship between a fundamental quantity of a first oscillating signal and a fundamental quantity of a second oscillating signal, and applying an adjustment to the first oscillating signal responsive to the relationship prediction to produce an adjusted oscillating signal, wherein the adjusted oscillating signal replaces the second oscillating signal.

Abstract: A field-effect transistor with a fail-open safety feature. A ferroic bridge extends between a source and a gate. The ferroic bridge includes a ferroic material that is in an electrically non-conducting state below a threshold temperature and in an electrically conducting state at and above the threshold temperature. When the ferroic bridge reaches the threshold temperature, the material switches to the electrically conducting state which electrically connects the source and the gate and restricts an electrical current from flowing through the field-effect transistor. The threshold temperature may be above a normal operating temperature and below a critical temperature at which a structural failure may occur. A reset terminal may allow for applying a reset signal that switches the ferroic material back to the non-conductive state to allow the current to resume flowing. The electrical signal may be applied perpendicular to a polarization of the ferroic bridge.

Abstract: A computer-implemented method for storing data in a memory device that includes a plurality of planes of data storage, with each plane including a plurality of blocks of data storage, comprises identifying a plurality of defective blocks within the memory device; and issuing a multiplane program command that includes the actual data to be stored in one or more viable plane(s) and false data to be stored in one or more defective plane(s), the one or more defective plane(s) each including one or more of the plurality of defective blocks.

Abstract: A trench metal oxide semiconductor field-effect transistor with a gate oxide stack, and a method of making a trench metal oxide semiconductor field-effect transistor with a gate oxide stack. A first layer of gate oxide is deposited on a surface of the trench using an atomic layer deposition or molecular vapor deposition process. A second layer of gate oxide is deposited on the first layer using a plasma-enhanced chemical vapor deposition process. The first and second layers of gate oxide are thermally annealed in a non-oxidizing atmosphere with a forming gas. Prior to depositing the first layer, the surface of the trench may be etched, an initial layer of thermal oxide may be deposited, and the initial layer may be nitridized or thermally annealed. If the initial layer is deposited on the surface of the trench, then the first layer is deposited on the initial layer.

Abstract: An apparatus includes a field-effect transistor (FET) and a physically and functionally integrated Schottky barrier diode located outside of the unit cell of the FET. A method of making the apparatus is also disclosed. The FET includes a source located at a first end of a volume of semiconductor material, a drain, and a channel for charge carriers moving therebetween. A gate is located adjacent the first end for facilitating controlling movement of the charge carriers through the channel.

Abstract: A computer-implemented method for training a machine learning model comprises receiving a first dataset related to first threshold voltages and first read error totals for a first memory cell type of the memory device, the first memory cell type having a first data storage capacity; receiving a second dataset related to second threshold voltages and second read error totals for a second memory cell type of the memory device, the second memory cell type having a second data storage capacity which is greater than the first data storage capacity; and training the machine learning model based on the first dataset and the second dataset, the trained machine learning model being configured to determine the threshold voltage for use with one or more memory cell(s) of the second memory cell type based on input data from one or more memory cell(s) of the first memory cell type.

Abstract: An apparatus that includes a beamforming antenna is provided. The apparatus may include a predictive calculator processing unit to receive position information of one or more airborne receivers, determine future position information of the one or more airborne receivers as a function of time based on the received position information, and determine beamforming antenna parameters. The apparatus may include an antenna instruction processing unit to receive the beamforming antenna parameters and generate beamforming instructions based on the beamforming antenna parameters, a beamforming antenna to receive the beamforming instructions, and to generate a beam at a specified time based on the beamforming instructions to enable communication with at least one of the one or more airborne receivers, and a receiver processing unit to receive airborne receiver data from the at least one of the one or more airborne receivers, and generate output data based on the airborne receiver data.

Abstract: A Controller Area Network (CAN) bus driver for driving a CAN bus is provided. The bus driver may include a first translinear loop circuit to receive an input voltage and output a first output current signal corresponding to an exponential function, a second translinear loop circuit to receive the input voltage and output a second output current signal corresponding to a hyperbolic function, a divider circuit to output a divided output current signal corresponding to the first output current signal divided by the second output current signal, a CAN Lo driver circuit to output the divided output current signal to a CAN Lo wire of the CAN bus, and a CAN Hi driver circuit to output the divided output current signal to a CAN Hi wire of the CAN bus.

Abstract: A smart cable for backplane storage management is provided. The cable may include a microcontroller, a power conditioning circuitry to regulate an input voltage from a power supply and provide an output voltage to the microcontroller, a storage device coupled to the microcontroller, a first end to be coupled to one or more storage devices, and a second end to be coupled to a storage controller. The microcontroller may receive sideband signals from the one or more storage drives, and may transmit connection topology information to the storage controller based at least in part on the sideband signals.

Abstract: A computer-implemented method and media for efficient power management of a data storage device including: receiving a host read request, identifying a virtual block (VB) included in the data storage device based on the host read request; determining an open block state of the identified VB, and performing a read operation on the identified VB corresponding to the host read request based on the determined open block state of the identified VB.

Abstract: A Peripheral Trigger Generator (PTG) for generating signals adaptively responsive to time-driven events based on execution run time. A variable PTG step delay, such as a “wait for software trigger” command, may provide an adaptive step delay between the output trigger commands. An adaptive step delay may use a combination of PTG Command+Control Bit in PTG Special Function Register. The adaptive step delay may be part of the Functional Safety Diagnostics package developed for the PTG module.

Abstract: In some implementations, a controller may receive a command to perform an erase operation to erase data stored in a block of a non-volatile memory device. The controller may determine a size of the data identified by the command. The controller may provide, based on the size of the data, a programming pulse to a location, of the block, that stores the data, wherein the programming pulse is provided to write predetermined data at the location. The controller may perform an erase operation on the block after writing the predetermined data.

Abstract: A controller for a motor system includes an input terminal to receive a signal indicating a speed of an electric motor and a regenerative brake current interpolator to indicate a brake current to be applied to the electric motor responsive to the speed of the electric motor. Values of the brake current vary with variation of the speed of the electric motor.

Abstract: A data storage system includes a memory device, a memory including instructions stored thereon, and at least one processor. The memory device includes a block that may include a plurality of wordlines (WLs). The memory includes instructions stored thereon that, when executed by the at least one processor, cause the at least one processor to: identify a plurality of data retention temperatures determined for the block at a plurality of corresponding times; compute an adjusted pass-through voltage (Vpassr) based on the plurality of data retention temperatures; and perform a read operation at least in part by: applying a read voltage (Vread) to a selected WL of the plurality of WLs; and applying the adjusted Vpassr to one or more unselected WLs of the plurality of WLs.