Abstract: Methods of using vapor cells may involve providing a vapor cell including a body defining a cavity within the body. At least a portion of at least one surface of the vapor cell within the cavity may include at least one pore having an average dimension of about 500 microns or less, as measured in a direction parallel to the at least one surface. A vapor pressure of a subject material within the cavity may be controlled utilizing the at least one pore by inducing an exposed surface of a subject material in a liquid state within the at least one pore to have a shape different than a shape the exposed surface of the subject material in a liquid state would have on a flat, nonporous surface.

Abstract: A system and method of testing an integrated circuit provide a first clock signal to a first flip-flop with an output to a functional circuit, provide a second clock signal to a second flip-flop with an input from the functional circuit, wherein the second flip-flip has a minimum hold time, provide a test input to the first flip-flop, observe a signal propagation time through the functional circuit, determine the signal propagation time is less than the minimum hold time of the second flip-flop, and increasing a timing separation by adding a unit of delay to the first clock signal or subtracting a unit of delay from the second clock signal.

Abstract: An apparatus includes an apparatus input to receive a voltage input, an apparatus output to drive an output metal oxide semiconductor field effect transistor (MOSFET) at least partially based upon the voltage input, a current source circuit to provide a current source to the apparatus output when the voltage input rises above a first threshold and before the voltage input rises above a second threshold, a voltage clamp circuit to provide a clamped output voltage to the apparatus output when the voltage input rises above the second threshold, and a current sink circuit to provide a current sink to the apparatus output when the voltage input falls below the second threshold and before the voltage input reaches the first threshold.

Abstract: Some disclosed embodiments relate, generally, to shaping a waveform of a reference signal used by a driver of a touch sensor to limit electromagnetic emissions (EME) emitted by a touch sensor during a sensing operation. Some disclosed embodiments relate, generally, to a DAC referenced touch sensor driver and controlling an amount of EME emitted at a touch sensor using shapes of reference signals used by a touch detector to detect touches at the touch sensor. Some disclosed embodiments relate, generally, to compensating for effects of foreign noise at a touch sensor and, more specifically, to changing a shape of a reference signal based on a change to a sampling rate made to compensate for foreign noise.

Abstract: An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.

Abstract: A system may include a communication circuit as part of a microcontroller. One or more registers may be configured to enable communication between the communication circuit and one or more external peripherals without a CPU or other processor controlling the communication. The one or more registers may be configured to allow a specific trigger event to initiate communication between the communication circuit and the external peripheral. A DMA controller may transmit data from the communication circuit to a memory and may transmit data from the memory to the external peripheral.

Abstract: Various embodiments relate to classifying comparators based on comparator offsets. A method may include applying, via a strobe, a first voltage to each of a first input and a second input of a comparator to generate a number of output signals from the comparator, wherein each output signal has one of a first polarity and a second polarity. The method may further include in response to each of the number of output signals being the first polarity, applying, via a strobe, an external offset voltage having the second polarity to the comparator to generate a second number of output signals. Further, the method may include in response to each of the second number of output signals being the same polarity, identifying the comparator as a reliable comparator.

Abstract: A multi-phase power converter with current matching is provided. The apparatus may include a control circuit to control a first phase of a power converter having a plurality of phases, and a phase matching circuit. The phase matching circuit may remove a DC component from an output ripple voltage of the converter, detect when respective ones of the plurality of phases begins generating its respective phase current and output a phase detector signal, extract a signal proportional to the first phase current and a signal proportional to either the remaining or total phase currents, output first and second voltages respectively proportional to the average of the first phase current and the remaining or total phase current, and output a corrective signal based on the difference between the first and second voltage. The control circuit may control the first phase based on the corrective signal.

Abstract: Various examples may include an apparatus including a memory to store ingressing data or egressing data, a timer to generate a timing signal responsive to a user-configurable time interval, and a circuit to move the ingressing data or the egressing data from the memory at least partially responsive to the timing signal generated by the timer. Various examples may include a method including receiving a data packet at a network-facing interface, writing data of the data packet into a memory, receiving a timing signal, and responsive to the timing signal, providing the data from the memory at a device-facing interface. Various examples may include a method including receiving data at a device-facing interface, writing the data to a memory, receiving a timing signal, and responsive to the timing signal, providing a data packet including the data at a network-facing interface. Related devices, systems and methods are also disclosed.

Abstract: Disclosed embodiments relate, generally, to improved data reception handling at a physical layer. Some embodiments relate to end of line systems that include legacy media access control (MAC) devices and PHY devices that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of legacy systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

Abstract: Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

Abstract: Systems for authenticating a file are disclosed. A system may include one or more physical devices. The one or more physical devices may select, based on an identifier, a subset of data segments of a computer file for generating a first digest with a cryptographic function. The one or more physical devices may also execute the cryptographic function on the selected subset of data segments of the computer file to generate the first digest. Further, the one or more physical devices may generate an authenticator based on the first digest and a private key. The one or more physical devices may further send the computer file, the identifier, and the authenticator to a secure node. Associated methods and non-transitory machine-readable medium are also disclosed.

Abstract: Systems having a capacitive touch sensing system with transmit and receive electrodes positioned to have mutual capacitances at node intersections that deviate when a node is touched; a processor; and a machine readable storage medium with instructions to: assign complete code words to transmit electrodes; identify a subset of transmit electrodes based on a prior touch position estimate; generate a transmit signal for the transmit electrodes; receive a first portion of a receive signal for receive electrodes indicative of capacitances; decode the first portion of the receive signal of receive electrodes using the first portions of the code words; and compute touch position estimates for the subset of transmit electrodes based on the decoded first portions of the receive signals.

Abstract: A circuit for electrostatic discharge (ESD) protection may protect sensitive circuits in the presence of both positive and negative ESD events. A protection transistor may be coupled to a pad, and a protection clamp may be coupled to the protection transistor. The protection transistor may be in an isolation n-well, and a current limiting resistor may be coupled from the pad to the isolation n-well. In operation, the current limiting resistor may limit the current during negative ESD events.

Abstract: An EtherCAT device with a node for use in an EtherCAT network is disclosed. The EtherCAT device includes: a clock circuit; a clock input to receive an input clock signal; a clock output to send an output clock signal; and control logic. The control logic is to determine whether to operate the EtherCAT device in a clock generation mode or a clock propagation mode, wherein in the clock generation mode, the clock circuit is to drive an oscillator to generate the input clock signal; and in the clock propagation mode, the clock circuit is to receive the input clock signal from another node in the EtherCAT network. The control logic is further to control the clock circuit to output the output clock signal for a subsequent node in the EtherCAT network based upon the input clock signal.

Abstract: An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory.

Abstract: A device includes a high-voltage amplifier to amplify a bursted signal and may couple to a driver circuit to drive a piezoelectric actuator. During the on-time of the bursted signal, a feedback circuit may compensate for non-idealities in the system and may equalize the signal at the actuator and the output of the high-voltage amplifier. During the off-time of the bursted signal, a signal conditioning circuit may sense a difference signal between the signal at the actuator and the signal at the high-voltage amplifier output and may interpret this difference signal as pressure applied to the piezoelectric actuator.

Abstract: An apparatus for inductive linear-position sensing is disclosed. An apparatus may include a support structure and an electrically conductive material defining a continuous path for electrical current to flow between a first location and a second location. The continuous path may include: a first path portion defining a first spiraling path for the electrical current to flow in a clockwise direction around a first axis; a second path portion laterally spaced from the first path portion and defining a second spiraling path for the electrical current to flow in a counter-clockwise direction around a second axis; a first coupling portion coupling an inner portion of the first path portion to an inner portion of the second path portion; and a second coupling portion coupling an outer portion of the second path portion to an outer portion of the first path portion. Related systems, devices, and methods are also disclosed.

Abstract: A device and method for sigma-delta modulation may include an input signal and a plurality of integrators. The output of the integrators and a data input may be input to an adder, the sum output to be input to a quantizer to generate a quantized output signal. A reset input to the first integrator may be asserted during a first sample of the quantized output signal to reduce the signal discontinuity at the input of the first integrator, which improves the stability of the sigma-delta modulator.

Abstract: Interposers and methods for making interposers having a substrate having a surface defining a plane; a first portion of a metal line directly or indirectly supported by the substrate; a barrier layer on the first portion of the metal line; a second portion of the metal line on the first barrier layer, wherein the second portion is opposite the first portion across the barrier layer. The method includes etching a line pattern in a first portion of a metal layer through a first photoresist layer to form a first portion of a metal line, depositing a barrier layer on the first portion of the metal line, and etching a line pattern in a second portion of the metal layer through a second photoresist layer to form a second portion of a metal line wherein the second portion is opposite the first portion across the barrier layer.