Abstract: A High-Electron-Mobility-Transistor that may include a substrate with a buffer layer formed on the substrate. A recess formed in the buffer layer. A barrier layer formed on the buffer layer. A gate recess formed in the barrier layer, the gate recess overlaps the recess in the buffer layer. A drain terminal formed at a first side of the barrier layer. A source terminal formed at a second side of the barrier layer. An isolation structure formed within the gate recess proximate the drain terminal. A doped structure formed adjacent to the isolation structure within the gate recess proximate the source terminal. A gate terminal formed on the doped structure.

Abstract: A Controller Area Network (CAN) bus driver for driving a CAN bus is provided. The bus driver may include a first translinear loop circuit to receive an input voltage and output a first output current signal corresponding to an exponential function, a second translinear loop circuit to receive the input voltage and output a second output current signal corresponding to a hyperbolic function, a divider circuit to output a divided output current signal corresponding to the first output current signal divided by the second output current signal, a CAN Lo driver circuit to output the divided output current signal to a CAN Lo wire of the CAN bus, and a CAN Hi driver circuit to output the divided output current signal to a CAN Hi wire of the CAN bus.

Abstract: A transistor comprising a drain layer, a drift layer over the drain layer, a channel layer over the drift layer, and a source layer over the channel layer. A trench formed through the source layer, through the channel layer and into at least partially the drift layer. A gate formed within the trench.

Abstract: A termination structure for a semiconductor device that may include a substrate having a first type dopant. A plurality of doped-wells having a second type dopant formed in the substrate. A plurality of trenches formed into the plurality of doped-wells, respective ones of the formed trenches exposing a bottom surface of the doped-well, and exposing side surfaces of the doped-well, and a material within respective ones of the formed trenches, wherein the material in respective ones of the formed trenches is surrounded by the exposed bottom surface of the doped-well of the respective formed trench and the exposed side surfaces of the doped-well of the respective formed trench.

Abstract: An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window based upon a first time measurement and a first previous time measurement received m time measurements earlier than the first time measurement. The sampling circuit is to generate a second sampled window based upon a second time measurement and a second previous time measurement received m time measurements earlier than the second time measurement. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.

Abstract: A method is provided that may include receiving an identifier of a permanent magnet synchronous motor (PMSM), and mapping the identifier to electrical parameters of the PMSM. The method may include determining one or more coefficients of a sliding mode observer (SMO) based on the electrical parameters. The method may include providing the determined coefficients to the SMO to estimate the rotor position and speed of the PMSM.

Abstract: An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window from the clock signal input. The first sampled window includes an accumulation of the N time measurements. The sampling circuit is to generate a second sampled window from the clock signal input including an accumulation of a plurality of products. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.

Abstract: A gate driver circuit to receive an input drive signal and output an output drive signal is provided. The gate driver circuit may include a first capacitor having first and second terminals, a second capacitor having first and second terminals, a first set of switches to selectively couple the first terminals of the first and second capacitors to the input drive signal and a power supply voltage, a second set of switches to selectively couple the second terminals of the first and second capacitors to a reference voltage and a high impedance node, and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high impedance node. The comparator may output the output drive signal based on a comparison of the reference voltage and a voltage at the high impedance node.

Abstract: An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first and second sampled window from the clock signal input. The first sampled window includes a sum of a plurality of a first m of the N time measurements. The second sampled window includes a sum of a plurality of a last m of the N time measurements. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.

Abstract: A trench power semiconductor device comprising a silicon carbide drain layer, a silicon carbide drift layer over the silicon carbide drain layer and a first silicon layer over the silicon carbide drift layer. A second silicon layer over the first silicon layer with a source silicon carbide layer over the second silicon layer. A trench formed through the source silicon carbide layer, through the second silicon layer and into at least partially the first silicon layer. A gate terminal contact formed on the trench with a drain terminal contact formed on the silicon carbide drain layer.

Abstract: Systems and methods for controlling an air flow rate provided to a burner based on the concentration of one or more gases provided to the burner are disclosed. A method for controlling a burner including receiving a gas concentration value indicating a concentration of one or more gases in a gas mixture provided to a burner; determining, using the gas concentration value, an air flow rate to input to the burner; and controlling the air flow rate provided to the burner based on the determined air flow rate.

Abstract: A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.

Abstract: A temperature sensor integrated in a transistor array, e.g., metal-oxide-semiconductor field-effect transistor (MOSFET) array, is provided. The integrated temperature sensor may include a doped well region formed in a substrate (e.g., SiC substrate), a resistor gate formed over the doped well region, first and second sensor terminals conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor includes a gate driver to apply a voltage to the resistor gate that affects a resistance of the doped well region below the resistor gate, and temperature analysis circuitry to determine a resistance of a conductive path passing through the doped well region, and determine a temperature associated with the transistor array.

Abstract: Systems and methods for communicating brain waves or control signals via body communication from the brain to body extremities to control or activate body parts or even external devices. An EEG coupler/transceiver couples to a person's scalp, wherein the EEG coupler/transceiver comprises an EEG electrode to receive a brain wave from the person, an EEG body communication coupler and an EEG antenna to transmit a signal via the EEG body communication coupler. An activator coupler/transceiver couples to the person's body to stimulate a muscle of the person's body, wherein the activator coupler/transceiver comprises a muscle activator, an activator body communication coupler, and an activator antenna to receive the signal via the activator body communication coupler.

Abstract: An apparatus may be communicatively coupled to other nodes in a network. The apparatus may include a control circuit configured to repeatedly issue transmission cycles to the other nodes. A given transmission cycle may include a least one send slot for each of the other nodes to send data. The control circuit may be configured to initiate transmission cycles by issuing beacon signals to the other nodes. The control circuit may be configured to determine when to issue a beacon signal in a given transmission cycle by determining that all of the other nodes have completed all associated send slots in an immediately previous transmission cycle and based upon a determination of the completion of the other nodes' transmission, delaying transmission of the beacon signal for the given transmission cycle.

Abstract: An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.

Abstract: Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

Abstract: Common view time transfer and related apparatuses and methods are disclosed. An apparatus includes a receiver oscillator to provide a local clock signal and one or more processors. The one or more processors are to perform, at least partially based on the local clock signal, event time tagging pre-processing at least partially responsive to satellite signals received from one or more satellites to generate a decimated precision correction state estimate; determine, per satellite signal pseudo range residuals; determine a navigation engine clock state; perform a precision clock state pre-processing operation at least partially responsive to the navigation engine clock state and the decimated precision correction state estimate to generate a precision navigation clock state; and generate a common view real time report at least partially responsive to the per satellite signal pseudo range residuals and the precision navigation clock state.

Abstract: A smart cable for backplane storage management is provided. The cable may include a microcontroller, a power conditioning circuitry to regulate an input voltage from a power supply and provide an output voltage to the microcontroller, a storage device coupled to the microcontroller, a first end to be coupled to one or more storage devices, and a second end to be coupled to a storage controller. The microcontroller may receive sideband signals from the one or more storage drives, and may transmit connection topology information to the storage controller based at least in part on the sideband signals.

Abstract: A multi-channel ADC system may include a plurality of input channels coupled to input signals. A multiplexer may couple one or more of the plurality of input channels to one or more multiplexer output channels. A control circuit may be coupled between the multiplexer output channels and an ADC. In operation, a configuration setting may configure the multi-channel ADC system in one of a plurality of configurations, including but not limited to single-ended, differential, pseudo-differential and hybrid configurations. The ADC may convert the plurality of input channels based on the configuration setting.