Abstract: An apparatus that includes a semiconductor substrate having first and second gate trenches arranged in parallel and extending in a first direction, and first and second gate electrodes embedded in the first and second gate trenches, respectively, via a gate insulating film. Each of the first and second gate electrodes includes a first conductive film located at a bottom of the respective first and second gate trenches and a second conductive film stacked on the first conductive film. The second conductive film included in a first portion of the second gate electrode is thinner than the second conductive film included in a first portion of the first gate electrode which is arranged adjacently to the first portion of the second gate electrode in a second direction crossing to the first direction. The second conductive film is lower in work function than the first conductive film.

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

Abstract: An apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. The contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. The width of the lower conductive section on a first boundary between the lower and upper conductive sections in the first direction is greater than the width of the upper conductive section on the first boundary in the first direction and the width of the second conductive pattern on a second boundary between the contact plug and the second conductive pattern in the first direction.

Abstract: A device comprises vertically oriented transistors. The device comprises a pillar comprising at least one oxide semiconductor material, the pillar wider in a first lateral direction at an upper portion thereof than at a lower portion thereof, a gate dielectric material over sidewalls of the pillar and extending in the first lateral direction, and at least one gate electrode adjacent to at least a portion of the gate dielectric material. Related devices, electronic systems, and methods are also disclosed.

Abstract: Methods and apparatuses associated with surface cleaning are described. Examples can include detecting at a processing resource of a robot and via a temperature sensor of the robot, a temperature of a surface on which the robot is located. Examples can include the processing resource shutting down the robot in response to the temperature being at or above a particular threshold temperature, and the processing resource instructing the robot to clean the surface following a particular cleaning path using a vacuum, a scrubber, or both in response to the temperature being below a particular threshold temperature.

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material. A vertical extension of the doped material protrudes upward to an interface with the channel material at elevation within the stack structure (e.g., an elevation proximate or laterally overlapping in elevation at least one source-side GIDL region). The microelectronic device structure may be formed by a method that includes forming a lateral opening through cell materials of the pillar, recessing the channel material to form a vertical recess, and forming the doped material in the vertical recess. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

Abstract: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.

Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.

Abstract: Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.

Abstract: In various embodiments, techniques can be provided to address debug efficiency for failures found on an operational system. The techniques can utilize a real-time trigger to notify a memory device to dump an error log to timely capture all needed information. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate a trigger signal to the memory device. In response to identifying the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate message probability compute data based on encoded data (e.g., data encoded using one or more encoding techniques). The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate message probability compute data for a message probability compute (MPC) decoder. In this manner, neural networks or recurrent neural networks described herein may be used to implement aspects of error correction coding (ECC) decoders, e.g., an MPC decoder that iteratively decodes encoded data.

Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.

Abstract: A method includes receiving a request for an allocation of memory resources based on quality of service (QoS) parameters. The method further includes provisioning, via a QoS manager component, a plurality of physical functions to provide the requested allocation of resources. At least two of the plurality of physical functions can be provided to meet a QoS criteria.

Abstract: Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.

Abstract: Methods, systems, and devices for opportunistic data movement are described. A memory device may include a non-volatile memory and a volatile memory that operates as a cache for the non-volatile memory. The memory device may receive a write command from a host device. The write command may be associated with a row of a bank in a volatile memory. The memory device may write data associated with the write command to a buffer that is associated with the bank and that is coupled with the volatile memory. And the memory device may communicate the data from the buffer to the volatile memory based on the write command and before a pre-charge command for the row of the bank is received from the host device.

Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.

Abstract: A memory system can include a stack of memory dies such as including a primary die and two or more secondary dies. The primary die can communicate with an external host device and with the secondary dies. In an example, the primary die can issue a command to the secondary dies using a first command message that includes an opcode field specifying a memory operation, a first chip identification field specifying a selected first die of the secondary dies, and one or more operands. In an example, each of the secondary dies receives the same first command message.