Abstract: This document describes apparatuses and techniques for implementing data masking with pulse amplitude modulation (PAM) encoded signals of a memory circuit. In various aspects, a data mask function of a memory controller may use an unassigned or prohibited PAM signaling state for a set of data lines to indicate data masking to a memory device for a group of data bits. For example, the data mask function may alter a PAM symbol or signal level for at least one data line from a low-voltage state (L) or mid-voltage state (M) state to a high-voltage state (H), resulting in a PAM signaling state for the set of data lines that corresponds data mask indication for the group of data bits. By so doing, the data mask function may indicate data masking for the group of bits without a dedicated data mask signal line, which may enable improved per-line memory bandwidth.

Abstract: A plurality of device temperature values that are each indicative of a temperature at a respective device of a plurality of devices of a system is identified. A respective composite temperature threshold ratio is determined for each device of the plurality of devices. A respective normalization value based on the respective composite temperature threshold ratio and the respective device temperature value is determined for each device of the plurality of devices. A largest normalization value of the plurality of devices is determined. A composite temperature of the system based on the largest normalization value of the plurality of devices is set.

Abstract: Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.

Abstract: Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.

Abstract: A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

Abstract: System and techniques for variable execution time atomic operations are described herein. When an atomic operation for a memory device is received, the run length of the operation is measured. If the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. A result of the operation is queued until it can be written to the cache line. At that point, the cache line is unlocked.

Abstract: Methods, systems, and devices for data compression for mapping tables are described. A memory system may store a table that includes mappings between a set of logical block addresses and a set of physical block addresses. The table may be stored to volatile memory of the memory system and each entry may include a subset of physical block addresses and one or more logical block addresses that correspond to the subset of physical block addresses. In some implementations, a quantity of the entries that each include the subset of physical block addresses and the one or more logical block addresses may be determined based on dividing the set of physical block addresses by a factor. Similarly, a size of the entries may be determined based on dividing the set of physical block addresses by the factor.

Abstract: Implementations described herein relate to host device initiated low temperature thermal throttling. A memory device may receive, from a host device, a low temperature thermal throttling command that indicates for the memory device to initiate a thermal throttling operation based on a temperature of the memory device not satisfying a temperature threshold. The low temperature thermal throttling command may indicate an amount of dummy data to be moved from the host device to a particular location of the memory device associated with the thermal throttling operation. The memory device may perform the thermal throttling operation based on moving the dummy data from the host device to the particular location of the memory device. The memory device may complete the thermal throttling operation based on moving the amount of data from the host device to the particular location of the memory device.

Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

Abstract: Apparatuses, systems, and methods for powered down non-target on-die termination (NT-ODT adjustment). A memory device has NT-ODT powered down logic which couples a designated pin of the command address terminals to an ODT control circuit, bypassing the command decoder, when the memory device is in a powered down state. An NT-ODT adjustment command received along the designated pin causes the ODT control circuit to change a resistance of the termination circuit of the memory while it is in the powered down state.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving, from a memory sub-system controller, a first read command and a second read command; determining that the memory device is in a suspended state; and responsive to determining that a first address range specified by the first read command does not overlap with a second address range specified by the second read command, issuing, to the memory device, the first read command and the second read command collectively.

Abstract: Implementations described herein relate to memory device initialization. In some implementations, a memory device may perform a first initialization for a first set of memory resources, the first initialization being associated with a boot image initialization. The memory device may enable a sideband interface, for data transfer between the memory device and a host device, based on a completion of the first initialization. The memory device may perform a second initialization for a second set of memory resources that is larger than the first set of memory resources. The memory device may enable a peripheral component interconnect express interface, for data transfer between the memory device and the host device, based on a completion of the second initialization.

Abstract: A method includes: creating a logical-to-physical address translation (L2P) bitmap for each respective virtual block programmed across a plane of multiple dice of a memory device, each L2P bitmap identifying logical addresses, within each respective L2P table of a plurality of L2P tables, that belong to a respective virtual block; creating a virtual block (VB) bitmap for each respective L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table, of the plurality of L2P tables, based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular virtual block; and identifying and updating, by the processing device, an L2P bitmap associated with the particular virtual block for an L2P mapping corresponding to the entry.

Abstract: Methods, systems, and devices for memory system logical unit number (LUN) procedures are described. A memory system may receive an indication to convert a LUN for storing LBAs associated with an application from a first type to a second type, where the second type is associated with a higher performance defragmentation process than the first type. The memory system may perform defragmentation on data associated with the LUN based on converting the LUN to the second type. The memory system may determine whether the LBAs stored in the LUN are ordered based on the defragmentation, and the memory system may operate (e.g., execute) the application based on the LBAs being ordered.

Abstract: An apparatus can include a processor and a vehicular communication component. The vehicular communication component can be configured to generate a vehicular private key and a vehicular public key, provide the vehicular public key to a plurality of external communication components wherein each respective one of the plurality of external communication components is positioned on a different transportation assistance entity, provide data to at least one of the plurality of external communication components, receive, in response to providing the data, additional data from the at least one of the plurality of external communication components, wherein the additional data is encrypted using the vehicular public key, and decrypt the additional data using the vehicular private key.

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

Abstract: A method of forming an electronic device comprises forming a stack structure comprising vertically alternating insulative structures and additional insulative structures, and forming pillars comprising a channel material and at least one dielectric material vertically extending through the stack structure. The method comprises removing the additional insulative structures to form cell openings, forming a first conductive material within a portion of the cell openings, and forming a fill material adjacent to the first conductive material and within the cell openings. The fill material comprises sacrificial portions. The method comprises removing the sacrificial portions of the fill material, and forming a second conductive material within the cell openings in locations previously occupied by the sacrificial portions of the fill material. Related electronic devices, memory devices, and systems are also described.

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Conductive vias are formed that are individually directly electrically coupled to the another source/drain region. Conductor material is formed that is directly coupled to the one source/drain region. The conductor material is patterned in one direction to form horizontal lines of the conductor material that have a horizontal trench between immediately-adjacent of the horizontal conductor-material lines. In a self-aligned manner, digitlines are formed that are individually in individual of the trenches between the immediately-adjacent conductor-material lines.

Abstract: Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.

Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.