Abstract: Semiconductor devices including vertically-stacked combination memory devices and associated systems and methods are disclosed herein. The vertically-stacked combination memory devices include at least one volatile memory die and at least one non-volatile memory die stacked on top of each other. The corresponding stack may be attached to a controller die that is configured to provide interface for the attached volatile and non-volatile memory dies.

Abstract: Control logic in a memory device receives, from a requestor, a request to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored and performs, using previously configured read operation parameters, a first read operation to read the data and a write temperature associated with the data from the memory array. The control logic determines whether the previously configured read operation parameters satisfy a temperature criterion and responsive to determining that the previously configured read operation parameters do not satisfy the temperature criterion, configures the memory device with updated read operation parameters, and performs, using the updated read operation parameters, a second read operation to read the data from the memory array.

Abstract: A storage product manufactured as a computer component and configured to have: a secure memory region to store cryptographic keys; a network interface; a local storage device having a storage capacity accessible via the network interface; and a host interface to be connected to a local host system. The local host system can control access, made via the network interface, to the storage capacity without receiving a portion of storage access messages received in the network interface. The storage product includes an access controller configured to determine whether a message, received in the network interface from the computer network or in the host interface from the local host system, has a valid verification code according to the cryptographic keys; and if not, the message can be rejected, deleted, discarded, or ignored without further processing.

Abstract: An exemplary system includes a memory comprising an error correction code (ECC) circuit and a scrub circuit, The ECC, during a read operation corresponding to a first read command, detects and corrects an error in read data read from a target row of a memory cell array using an ECC and to provide corrected read data and a ECC error alert (EEA) signal having a value based on a number of errors detected in the read data. The scrub circuit, during the read operation and in response to self-scrub mode being enabled, causes the corrected read data to be written back to the target row of the memory cell array in response to the EEA having a scrub required value.

Abstract: Apparatuses, systems, and methods for algorithm qualifier commands are described according to embodiments of the present disclosure. One example method can include executing an algorithm qualifier command on a memory device and performing an operation on the memory device for a command sequence that follows the algorithm qualifier command using a number of settings indicated by the algorithm qualifier command. The algorithm qualifier command can indicate a number of settings to use while performing the operation on the memory device.

Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: In a computer host system, a system and method to compress the transmission between the central processing unit (CPU) and the dynamic random access memory (DRAM) of either of an extended consecutive series of ‘0’ bits or an extended consecutive series of ‘1’ bits. The CPU or a Compute Express Link (CXL) Initiator associated with the CPU identifies the consecutive strings of ‘0’ bits or ‘1’ bits. The CPU or the CXL Initiator sets data flags in a FLIT data structure, using just two bits or four bits to indicate the strings. The data structure is sent to a CXL memory, which interprets the flags and constructs the extended series of ‘0’ bits or extended series of ‘1’ bits.

Abstract: In some implementations, a device may obtain a command table associated with a memory device, wherein the command table includes one or more entries associated with one or more respective commands, and wherein each entry, from the one or more entries, includes one or more units of data. The device may receive an indication of a modification associated with a first command, wherein the first command indicates a sequence of a first one or more units of data. The device may modify the command table based on the modification associated with the first command, wherein modifying the command table includes at least one of: adding an entry, that indicates the sequence, to the one or more entries to indicate the first command, or removing the entry from the one or more entries. The device may provide, to a controller of the memory device, an indication of the command table.

Abstract: The present disclosure includes apparatuses and methods related to a memory apparatus and/or method for addressing in memory with a read identification (RID) number. An example apparatus can include a first memory device, a second memory device coupled to the first memory device, and a controller coupled to the first memory device and the second memory device, wherein the controller is configured to receive a read command requesting data from the first memory device, wherein the read command includes a read identification (RID) number that includes an address to identify a location of the data in the first memory device, and transfer the data from the location in the first memory device to the second memory device in response receiving the read command.

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs in a first vertical cross-section along a first direction. Insulating material is in the cavity above the flight of stairs. The insulating material comprises first material atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Insulative second material of different composition from that of the first material is directly above the first material. The first material has an uppermost surface in the cavity that is below an uppermost surface of the insulative second material in the cavity.

Abstract: Apparatuses, machine-readable media, and methods related to cleaning detection are described. A cleaning detection system can be used to determine whether there is a need for cleaning by comparing detection inputs, from sensors of the cleaning detection system, that are associated with an updated status of an area to a baseline status of an area. The cleaning detection system can receive a number of initial inputs associated with an area scanned by the device, determine a baseline status of the area based on the number of initial inputs, receive a number of detection inputs associated with the area scanned by the device, and determine whether a location of the area is in need of cleaning based on a comparison of the baseline status and the number of detection inputs.

Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.

Abstract: In some aspects, the techniques described herein relate to a device including: a storage device, the storage device including a first physically unclonable function (PUF) and configured to generate a storage device public key and a storage device private key; and a secure environment, the secure environment including a controller configured for: transmitting a nonce value to the storage device; receiving a response from the storage device, the response including a unique identifier (UID) and a digital signature, the digital signature generated using the UID and the nonce value; validating the digital signature using a public key of the storage device; and issuing a command to the storage device after validating the digital signature.

Abstract: Light emitting diodes (“LEDs”) with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. The method also includes forming an LED structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment.

Abstract: A microelectronic device package includes a microelectronic device, a masking material defined (MMD) contact, and a non-masking material defined (NMMD) contact. The microelectronic device is supported on, and electrically connected to, one of a package substrate and a redistribution layer. The MMD contact is located in a first region of the one of the package substrate and the redistribution layer and facilitates a first electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. The NMMD contact is located in a second, different region of the one of the package substrate and the redistribution layer and facilitates a second electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. Related methods and systems are also disclosed.

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material laterally offset from one another. The pillars have source/drain regions and channel regions vertically offset from the source/drain regions. Gating structures pass across the channel regions, and extend along a first direction. An insulative structure is over regions of the first and second pillars, and extends along a second direction which is crosses the first direction. Bottom electrodes are coupled with the source/drain regions. Leaker-device-structures extend upwardly from the bottom electrodes. Ferroelectric-insulative-material is laterally adjacent to the leaker-device-structures and over the regions of the bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material and is directly against the leaker-device-structures. Some embodiments include methods of forming integrated assemblies.

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may receive an access command transmitted to the memory device via a bus. The memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. The control signal may be transmitted during a first unit interval of a read operation. The control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. The control line may be configured to have or trend toward the first voltage when the bus is in the idle state.

Abstract: Methods, systems, and devices for memory operations are described. A host system may obtain data for writing to a memory system. The host system may send, to the memory system, an indication that the data is to be written to the memory system, and the memory system may remove invalid data at the memory system until the memory system has sufficient resources to store the data. Based on the memory system having sufficient resources, the memory system may delay background operations at the memory system until the data has been written to the memory system. The memory system may also create a restore point based on the memory system having sufficient resources and receiving the data. In other examples, the removal of invalid data at the memory system may be delayed until after the data is written to the memory system.