Abstract: Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of stadiums, within the stack structure, includes stadiums of differing numbers of staircase sets, such as a stadium having multiple parallel sets of staircases and an additional stadium having a single set of staircases. Each of the staircases includes steps, at ends of the conductive structures, with a same multi-tier riser height. In methods of fabrication, a same initial stadium opening may be concurrently formed for each of the stadiums—regardless of whether the stadium is to include the single set or the multiple parallel sets of staircases—with the steps of the same multi-tier riser height. Electronic systems are also disclosed.

Abstract: A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data. A source cursor associated with the victim MU is identified from an ordered set of cursors. A target cursor following the source cursor in the ordered set of cursors referencing one or more available MUs is identified. In response to determining that the source cursor is a last cursor in the ordered set of cursors, the source cursor is utilized as the target cursor. The valid data is associated with the identified target cursor.

Abstract: Methods, systems, and devices for circuit board structures for component protection are described. A memory system may be implemented on a circuit board, where one or more memory devices may be attached to the circuit board. Components for accessing the one or more memory devices may also be attached to the circuit board. The circuit board may also include one or more structures extending from the circuit board that are configured to shield the one or more memory devices, the components for accessing the one or more memory devices, or both, from forces.

Abstract: An electronic device comprises a source stack comprising one or more conductive materials. A source contact is adjacent to the source stack and a source seal is on a portion of the source contact. Tiers of alternating conductive materials and dielectric materials are adjacent to the source contact. Pillars extend through the tiers and the source contact and into the source stack. Additional electronic devices, electronic systems, and methods of forming the electronic devices are disclosed.

Abstract: A plurality of memory device life metrics are determined, where one of the plurality of memory device life metrics comprises a read count metric that specifies a number of read operations performed on the memory device. A plurality of normalized metric values are calculated, where each of the normalized metric values is based on a ratio of a respective memory device life metric to a respective lifetime target value associated with the respective memory device life metric. A normalized metric value that satisfies a selection criterion is identified from the plurality of normalized metric values. The identified normalized metric value corresponds to an amount of used device life of the memory device. An amount of remaining device life of the memory device is determined based on the identified normalized metric value. An indication of the amount of remaining device life is provided to a host system.

Abstract: Methods, systems, and devices for command prioritization techniques for reducing latency in a memory system are described. In some examples, a host system may receive a set of commands from one or more virtual machines to access a common memory system. The host system may store the set of command in a command queue associated with the memory system and arrange the set of command according to order that is based on one or more identified pattern of accessing sequential addresses in the set of commands. The host system may transmit the set of command to the memory system based on the order and the memory system may execute the commands according to the order.

Abstract: Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified and executed at a secure sub-system, an open sub-system can be put into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified and/or executed unless the open sub-system is put into the resume state again.

Abstract: A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions.

Abstract: A memory module includes a number of memory devices which receive refresh commands. Each memory device determines if it is that device's turn in a sequence, for example by counting the refresh commands. When it is not a device's turn, it performs refresh operations at a first rate responsive to the refresh commands. When it is the device's turn, it performs refresh operations at a second, lower, rate responsive to the refresh commands, for example by skipping refresh operations.

Abstract: Memory devices are disclosed. A device may include a number of word line drivers, wherein each word line driver of the number of word line drivers including a first transistor and a second transistor. The device may also include a number of first driver gates, wherein the first transistor of each word line driver has a gate coupled to a dedicated first driver gate of the number of driver gates. Further, the device may include a second driver gate coupled to a gate of each second transistor of each of the number of word line drivers. Associated circuits, methods, and systems are also disclosed.

Abstract: Methods, systems, and devices for auto-calibration of error detection signals are described. An error may be injected into a data signal obtained from a memory array. After injecting the error into the data signal, the data signal may be applied to an error detection circuit of the memory array, where the error detection circuit may output an error signal for the data signal. The error signal may be delayed relative to a control signal by a first amount. A timing signal that controls the propagation of the error signal may be obtained based on delaying the control signal by a second amount. Based on a comparison of the error signal and the timing signal, a third amount for delaying the control signal may be determined.

Abstract: This document describes apparatuses and techniques for implementing data masking with pulse amplitude modulation (PAM) encoded signals of a memory circuit. In various aspects, a data mask function of a memory controller may use an unassigned or prohibited PAM signaling state for a set of data lines to indicate data masking to a memory device for a group of data bits. For example, the data mask function may alter a PAM symbol or signal level for at least one data line from a low-voltage state (L) or mid-voltage state (M) state to a high-voltage state (H), resulting in a PAM signaling state for the set of data lines that corresponds data mask indication for the group of data bits. By so doing, the data mask function may indicate data masking for the group of bits without a dedicated data mask signal line, which may enable improved per-line memory bandwidth.

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. An anisotropically-etched spacer is formed extending along the first direction directly above the flight of stairs. The anisotropically-etched spacer is used as a mask while etching through one of the first tiers and one of the second tiers in individual of the stairs to form multiple different-depth treads in the individual stairs along a second direction that is orthogonal to the first direction. Individual of the treads comprise conducting material of individual of the first tiers in the finished-circuitry construction. Other aspects, including structure independent of method, are disclosed.

Abstract: Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.

Abstract: A plurality of device temperature values that are each indicative of a temperature at a respective device of a plurality of devices of a system is identified. A respective composite temperature threshold ratio is determined for each device of the plurality of devices. A respective normalization value based on the respective composite temperature threshold ratio and the respective device temperature value is determined for each device of the plurality of devices. A largest normalization value of the plurality of devices is determined. A composite temperature of the system based on the largest normalization value of the plurality of devices is set.

Abstract: A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.

Abstract: A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

Abstract: System and techniques for variable execution time atomic operations are described herein. When an atomic operation for a memory device is received, the run length of the operation is measured. If the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. A result of the operation is queued until it can be written to the cache line. At that point, the cache line is unlocked.

Abstract: Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.