Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating semiconductive tiers and intervening tiers. A horizontally-elongated trench extends vertically through the stack. Semiconductive material in individual of the semiconductive tiers comprises a top, a bottom, and a trench end extending between the top and the bottom. The trench end in the individual semiconductive tiers is masked to leave the top and the bottom unmasked. Through the trench, the semiconductive material is removed from the unmasked top and the unmasked bottom while the trench end is at least initially masked to vertically thin the semiconductive material in the individual semiconductive tiers. Additional embodiments are disclosed.

Abstract: Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, one or more physical column planes may be selectively configured to store metadata. Depending on the amount of metadata to be stored, the column selects may be arranged into virtual column planes to allow data to be stored in physical column plane(s) used for metadata. The physical column planes may be arranged into virtual planes to store the data. In some examples, data steering circuitry including multiplexers and tri-state drivers may be used to steer data between physical column planes to implement the virtual planes. In some examples, a column decoder may include multiplexers to remap logical addresses to implement the virtual planes.

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, one or more physical column planes may be selectively configured to store metadata. Depending on the amount of metadata to be stored, the column selects may be arranged into virtual column planes to allow data to be stored in physical column plane(s) used for metadata. The physical column planes may be arranged into virtual planes to store the data. In some examples, data steering circuitry including multiplexers and tri-state drivers may be used to steer data between physical column planes to implement the virtual planes. In some examples, a column decoder may include multiplexers to remap logical addresses to implement the virtual planes.

Abstract: Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory cell tiers individually comprise a horizontal transistor, a capacitor, and part of a digitline. The capacitor comprises a capacitor electrode that is common to a plurality of the memory cells. The common capacitor electrode comprises a void-space in individual of the insulative tiers. Other embodiments, including method, are disclosed.

Abstract: A memory device includes a memory array organized into banks, with each bank including a number of rows, each of which stores a number of codewords. Over the course an error check and scrub (ECS) cycle, ECS addresses for each codeword are sequentially generated and each codeword is checked for errors and those errors are corrected. One or more ECS operations may be performed responsive to an ECS command. The ECS command may specify address information about where the ECS operation(s) should be performed.

Abstract: In some aspects, the techniques described herein relate to a method including: generating a digital certificate using a public key of a secure environment; storing the digital certificate in a storage device of a cloud service; generating, by the secure environment, a signed command to access the storage device, the signed command signed using a private key corresponding to the public key of the secure environment; and issuing the signed command to the storage device to access data stored by the storage device.

Abstract: A method includes supplying, via a first voltage regulator, a first supply voltage to a first voltage domain including circuitry configured to operate at the first supply voltage, supplying, via a second voltage regulator, a second supply voltage to a second voltage domain including circuitry configured to operate in a voltage zone, detecting a change in an error characteristic of data associated with the second voltage domain, and altering the second supply voltage to an altered supply voltage based on the change in the error characteristic.

Abstract: An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.

Abstract: In some implementations, a memory device may allocate first credit amounts for respective physical functions from a set of physical functions associated with the memory device, wherein the first credit amounts correspond to allocations for one or more performance metrics for the set of physical functions over a time window. The memory device may allocate second credit amounts for the respective physical functions from the set of physical functions, wherein the second credit amounts correspond to allocations for the one or more performance metrics for virtual windows included in the time window, and wherein the second credit amounts are based on the first credit amounts and an amount of time associated with the time window. The memory device may perform, during each virtual window included in the time window, one or more operations associated with the set of physical functions based on the second credit amounts.

Abstract: Various embodiments provide for writing padding data to a memory device, such as a NOT-AND-type memory device, using an on-memory-device copy operation, which can be used as part of a memory system. According to some embodiments, writing padding data to one or more target blocks of a memory device comprises performing an on-memory-device copy operation to copy padding data (e.g., one or more pages of padding data) from a padding source (e.g., dedicated padding source block) on the memory device to the one or more target blocks (e.g., to one or more target pages of the one or more target blocks).

Abstract: A request can be provided, from a front-end of a memory sub-system, to a processing device of the memory sub-system and deleting the request from a buffer of the front-end of the memory sub-system. Responsive to deleting the request from the buffer, determining a first quantity of requests in the buffer and responsive to deleting the requests from the buffer, determining a second quantity of outstanding requests in the back-end of the memory sub-system. Responsive to deleting the request from the buffer and providing the request to the processing device, determining whether to provide a response to a host, wherein the response includes an indication of the quantity of requests in the buffer and of outstanding requests in a back-end of the memory sub-system, based on a comparison of the second quantity of outstanding requests to a threshold.

Abstract: A storage application running in a local host system connected to a storage product to define and implement at least a function, feature, or aspect of network storage services provided via the storage product. The storage application can specify a configuration for message selection performed in the storage product. A first message selected from incoming messages received in a network interface of the storage product is processed by the storage application to generate second messages. The processing of the second messages in the storage product implements a new function not available in the storage product standalone. Responses to the second messages can be selected for processing by the local host system, based on which the storage application can generate a response to the first message. The response can be sent back to the storage product for transmission using its network interface.

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes an electrically insulating material and bit lines including copper in the electrically insulating material. The electrically insulating material defines air gaps between the bit lines. A method of manufacturing a memory device includes forming trenches in an electrically insulating material on or in circuitry of the memory device, forming a first electrically conductive material in the trenches, removing portions of the electrically insulating material to form air gaps between the trenches, recessing the first electrically conductive material, and replacing the first electrically conductive material that was removed with a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. A memory device includes the apparatus.

Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.

Abstract: A system and method are disclosed for inexact search acceleration using reference data. A representative system includes one or more memory circuits storing a plurality of queries and a FM-index of the reference data; and one or more FPGAs configured to select a query; select a substring of the selected query; read a section of the FM-index and calculate a plurality of suffix array intervals for the sub string with a corresponding plurality of prepended characters in a first or next position; read a first or next character in the first or next position of the query and select a suffix array interval for the read first character; determine whether the suffix array interval is valid and whether a beginning of the query has been reached; returning a first search result when the suffix array interval is valid and the beginning of the query has been reached; and returning a second search result that no match of the query with the reference data was found when the suffix array interval is not valid.

Abstract: This disclosure is directed to a memory device that intelligently applies an additional read offset when reading memory blocks. The memory device receives a request to read a portion from a memory device and computes a read threshold voltage for reading data from the portion of the memory device. The memory device determines whether the portion is associated with a pseudo-folding event and, in response to determining whether the portion is associated with the pseudo folding event, selectively applies an additional read offset to the read threshold voltage to read the data from the portion of the memory device.

Abstract: Systems and methods are provided for using a 2.5D PHY and a 3D PHY for communications between a memory device and a host device. The memory device includes a 2.5D PHY for communications with the host device through a predefined communication interface and a 3D PHY for communications with the host device through a customized communication interface. The 2.5D PHY of the memory device is used for communications through the predefined communication interface when the customized communication interface is not available or undesired (e.g., during testing of the memory device).

Abstract: Enhancement or reduction of page migration can include operations that include scoring, in a computing device, each executable of at least a first group and a second group of executables in the computing device. The executables can be related to user interface elements of applications and associated with pages of memory in the computing device. For each executable, the scoring can be based at least partly on an amount of user interface elements using the executable. The first group can be located at first pages of the memory, and the second group can be located at second pages. When the scoring of the executables in the first group is higher than the scoring of the executables in the second group, the operations can include allocating or migrating the first pages to a first type of memory, and allocating or migrating the second pages to a second type of memory.

Abstract: Apparatuses, systems, and methods for a damper for a printed circuit board assembly (PCBA). One example apparatus can include a PCBA of a solid state drive (SSD) and a damper configured to contact the PCBA, contact an enclosure of the SSD, and damp shock impulses applied to the SSD.