Abstract: A variety of applications can include apparatus having a recessed channel FinFET. The recessed channel FinFET can include one or more fin structures between the source region and the drain region, where the one or more fin structures are recessed from a top level of the source region and from a top level of the drain region. The recessed channel FinFET can include a gate recessed from the top level of a source region and a drain region, where the gate can be separated from tip regions of the fin structures by a gate dielectric defining a channel between the source region and the drain region. Recessed channel FinFETs can be structured in a periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of cross correlation including symbols indicative of radio frequency (RF) energy. An electronic device including a statistic calculator may be configured to calculate a statistic including the cross-correlation of the symbols. The electronic device may include a comparator configured to provide a signal indicative of a presence or absence of a wireless communication signal in the particular portion of the wireless spectrum based on a comparison of the statistic with a threshold. A decoder/precoder may be configured to receive the signal indicative of the presence or absence of the wireless communication signal and to decode the symbols responsive to a signal indicative of the presence of the wireless communication signal. Examples of systems and methods described herein may facilitate the processing of data for wireless communications in a power-efficient and time-efficient manner.

Abstract: Apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. Shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. In example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. With the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.

Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells

Abstract: Apparatuses and methods including circuits in gap regions of a memory array are disclosed. An example apparatus includes first and second memory mats adjacent along a first direction, and further includes a region between the first and second memory mats along the first direction. The region includes a local input/output (LIO) line that extends along a second direction perpendicular to the first direction through the region, and further includes a LIO driver and a LIO precharge circuit coupled to the LIO line. The LIO driver is configured to drive the LIO line to data voltage levels based on data read from memory cells or based on data to be written to memory cells, and the LIO precharge circuit is configured to provide a LIO precharge voltage to the LIO lines.

Abstract: Described apparatuses and methods facilitate sharing redundant memory portions at a controller-level to enable memory repair between two or more memory blocks. Each memory die of multiple memory dies can include, for instance, multiple spare rows for use if a row of a memory array has a faulty bit. If a memory die has more faults than spare rows, the memory die cannot repair the additional faults. This document describes a controller that can inventory unrepaired faults and available spare rows across multiple memory dies. The controller can then “borrow” a spare row from a second memory die that has an available one and “share” the spare row with a first memory die that has a fault than it cannot repair. The controller can remap a memory access request targeting the row with the unrepaired fault in the first memory die to a spare row in the second memory die.

Abstract: Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an ×4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Abstract: Examples of systems and method described herein or generating, in a memory controller and/or memory device, access codes for memory regions of the memory device using authentication logic, and for accessing the memory device using the access codes. For example, a memory controller and/or a coupled memory device may generate access codes that a host computing device may include in a memory access request to access one or more memory regions of the memory device. Data read or written at the memory device may in some examples only be accessed in accordance with the access codes for memory regions of the memory device. Accordingly, the systems and methods described herein may provide security for specific memory regions of a memory device because the access code are updated periodically (e.g., based on obtained reset indication) or in accordance with an updated count value from a counter.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.

Abstract: The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to drive an access line of the memory array to a discharging voltage during an IDLE phase, to drive said access line to a floating voltage during an ACTIVE phase, and to drive said access line at least to a first or second read/program voltage during a PULSE phase.

Abstract: A cache memory having a memory media device row activation-biased caching policy is described. The cache policies that are biased based on row activation counts include at least one of a cache line eviction policy which determines which cache lines are the most evictable from the cache memory, and cache line storage policy which determined which row data is allocated cache lines for storage. A memory controller including a row activation-biased cache memory is also described. The memory media device may be DRAM.

Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

Abstract: An image or a spectrum of a surface may be acquired by a computing device, which may be included in a mobile device in some examples. The computing device may extract a measured spectrum from the image and generate a corrected spectrum of the surface. In some examples, the corrected spectrum may be generated to compensate for ambient light influence. The corrected spectrum may be analyzed to provide a result, such as a diagnosis or a product recommendation. In some examples, the result is based, at least in part, on a comparison of the corrected spectrum to reference spectra. In some examples, the result is based, at least in part, on an inference of a machine learning model.

Abstract: Methods, systems, and devices for virtualized authentication device are described. A virtual device (such as a virtual machine) may be permitted to access secured data within a memory device by an authentication process. The memory device may generate cryptographic keys in portions of the memory device and assign the cryptographic keys to the virtual machines. The virtual machine may use an authentication process using the cryptographic keys to access the secure data in the memory device. The authentication process may include authenticating the identity of the virtual machine and the code operating on the virtual machine based upon comparing cryptographic keys received from the virtual machines to the assigned cryptographic keys in the partitions of the memory device. Once both the identity of the virtual machine is authenticated, the virtual machine may be permitted to access the secure data in the memory device.

Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.

Abstract: Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

Abstract: Systems, apparatuses, and methods related to memory bank protection are described. A quantity of errors within a single memory bank is determined and the determined quantity is used to further determine whether to access other memory banks to correct the determined quantity. The memory bank protection described herein avoids a single memory bank of a memory die being a single point of failure (SPOF).

Abstract: Various embodiments described herein provide a label configured for thermal conductivity and configured to pass over an edge of a printed circuit board (PCB) and attached to both sides of the printed circuit board. The label can be used with a printed circuit board that is associated with a memory sub-system, such as a memory module (e.g., solid state drive, SSD module).

Abstract: Methods, systems, and devices for device reset alert mechanism are described. The memory system may identify a fault condition associated with resetting the memory system and set, in a register associated with event alerts of the memory system, a first indication for a reset of the memory system. In some cases, the memory system may transmit a message that includes a second indication that the register associated with event alerts of the memory system has been changed based on setting the register. The memory system may reset one or more components of the memory system based on the first indication and the second indication.

Abstract: Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.