Abstract: Apparatuses and techniques for performing serialized update procedures during a refresh period are described. In example aspects, a memory device performs a normal refresh operation, which refreshes multiple rows simultaneously. The refreshed rows are associated with different refresh sections and different column segments. While refreshing the rows and prior to an end of a refresh cycle time (tRFC), the memory device updates, in a serialized manner, usage-based-disturbance data that is stored within the refreshed rows. In particular, the memory device performs, in series, multiple update procedures, which overwrites values of the usage-based-disturbance data that are stored within the refreshed rows. For example, the multiple update procedures can set values of activation counts that are stored within the refreshed rows to a predetermined value.

Abstract: A memory device can include one or more core dies and an interface die. A read clock signal having a first frequency may be generated on the interface die and provided to circuitry on the interface die. The read clock signal is provided from the interface die to the core die(s). Access operations (e.g., read operations) are performed on a memory array on at least one core die based on the read clock signal. The data read from the memory array(s) is provided to the interface die. A data clock signal having a second frequency is generated on the interface die based on the read clock signal. The read data is output from the interface die based on the data clock signal. In some instances, pulses in the data clock signal are aligned with rising and falling edges of the pulses in the read clock signal.

Abstract: Systems and methods include receiving data bits at an input pin of a semiconductor device from a host device. The received data is latched in latch circuitries of the semiconductor device that at least partially implements an equalizer to aid in interpreting the received data bits. A first latched bit latched from the first received bit of the received bits is transmitted from the latch circuitries to self-calibration circuitry. The first received bit is also latched in error evaluation circuitry as a second latched bit. The second latched bit is transmitted from the error evaluation circuitry to the self-calibration circuitry. The self-calibration circuitry determines settings for the equalizer without involving the host device in determining the settings after the host device sends the data bits.

Abstract: Methods, systems, and devices for address mappings for random access operations are described. A portion of a L2P table may be loaded (e.g., to a buffer) upon receiving a write command (e.g., a random write command). In some instances, one or more entries (e.g., one or more mappings) included in the portion of the L2P table may be updated based on the write command. The portion of the L2P table may be maintained in the buffer during subsequent access operations, such as random read operations. The subsequent access operations may utilize the portion of the L2P table to access a memory device.

Abstract: A method includes receiving, by a memory device interface, a signal at a front side of a command enable channel from a host, locking, by the memory device interface, a back side of a command enable channel in response to the signal, receiving, by the memory device interface, the command at a data channel from the host, and unlocking, by the memory device interface, the back side of the command enable channel in response to receiving the command at the data channel.

Abstract: Methods, systems, and devices for block repurposing based on health metrics are described. The method may involve setting a storage state of a block of memory cells, the storage state corresponding to a storage density of the block of memory cells or an access mode of the block of memory cells. Further, the method may involve updating the storage state of the block of memory cells based on a health condition associated with the block of memory cells and accessing the block of memory cells based on the updated storage state of the block of memory cells.

Abstract: A memory device can include a memory array including a plurality of memory cells coupled to a control logic. The control logic is to initiate a program operation on one or more memory cells of a first segment of the memory array, wherein the program operation comprises a first calibration phase. The control logic can also read a first stored value corresponding to a first voltage applied during a second calibration phase for a second segment of the memory array, the second calibration phase before the first calibration phase. The control logic can further read a second stored value corresponding to an offset value associated with the first voltage. Additionally, the control logic can determine a second voltage for application during the calibration phase responsive to reading the first stored value and the second stored value.

Abstract: Modular systems in packages, and associated devices, systems, and methods, are disclosed herein. In one embodiment, a system comprises a main module package and an upper module package. The main module package includes a first substrate and a first electronic device mounted on a first side of the first substrate. The upper module package includes a second substrate and one or more second electronic devices mounted on a first side of the second substrate. The second substrate includes a cavity at a second side of the second substrate opposite the first side, and the upper module package is mountable on the first side of the first substrate of the main module package such that the first electronic device is positioned within the cavity and the second substrate generally surrounds at least a portion of a perimeter of the first electronic device.

Abstract: A memory card, for use with a host system, combines both: (i) non-volatile memory express (NVMe) data storage such as a solid state drive (SSD) with (ii) dynamic random access memory (DRAM) conforming to the computer express link (CXL) protocol. The SSD and CXL DRAM share a common controller. CXL memory requests from the host system are handled according to the CXL.io protocol. NVMe data requests are wrapped into a CXL request packet. The common front end identifies the NVMe data request(s) within the CXL packet, parses the NVMe data request, and routes the request to the NVMe memory. A host operating system software driver intercepts the NVMe memory requests and wraps them into the CXL request packet.

Abstract: The disclosure configures a memory sub-system controller to efficiently perform block migration (e.g., from SLC cache to QLC blocks) in a Zone Namespace (ZNS) device. The controller associates a plurality of zones of the set of memory components with a plurality of internal zone groups (IZGs) each associated with a different write cursor. The controller programs data to a first portion of a set of memory components using the plurality of write cursors, the first portion being associated with a first type of storage, and determines that an individual IZG of the plurality of IZGs satisfies a migration criterion. The controller migrates a portion of the data stored in the first portion of the set of memory components corresponding to the individual IZG to a second portion of the set of memory components, the second portion of the set of memory components being associated with a second type of storage.

Abstract: The present disclosure is directed to routing of data in a spiking neural network (SNN) that performs in-memory operations. To model a computer-implemented SNN after a biological neural network, the architecture in the present disclosure involves different memory sections for storing inbound spike messages, synaptic connection data, and synaptic connection parameters. Embodiments are directed to routing spike messages through various router-based topologies. For example, spike messages may be multicasted to target routers using address tables.

Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

Abstract: Processing can occur in registers of a memory sub-system. A first plurality of registers coupled to the plurality of sense amplifiers can store the first plurality of bits received from the plurality of sense amplifiers. Processing circuitry coupled to the first plurality of registers can receive the first plurality of bits from the first plurality of registers and can perform an operation on the first plurality of bits to generate result bits. A second plurality of registers coupled to the processing circuitry and the plurality of registers can store the result bits received from the processing circuitry and can provide the result bits to a plurality of data input/output (I/O) lines prior to storing a second plurality of bits.

Abstract: A request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. A bitline voltage adjustment value based on a number of program erase cycles (PECs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. A default bitline voltage is adjusted by the bitline voltage adjustment value to generate an adjusted bitline voltage. The program operation on the set of vertically stacked memory cells is performed using the adjusted bitline voltage.

Abstract: This document describes apparatuses and techniques for an efficient command protocol for memory access. In various aspects, a memory controller may implement combined operations of different command types (e.g., an activation command plus a read, an activation command plus a write, or an activation command plus a pre-charge command) to better utilize a multiple clock ratio of a command bus (e.g., a (1.5+0.5)N operation in a dual clocking WCK2CK ratio of 4:1), which may improve utilization of a data bus for associated memory responses. By so doing, the efficient command protocol may improve power efficiency and system level performance of a computing system.

Abstract: A method for managing data in a non-volatile memory system includes generating, by a randomizer integrated on a die of a memory device, padding data to close a memory block for a data write operation. The padding data is random data. The method includes programming, by a media controller of the memory device, the padding data into specified memory pages in a data block within the memory device. The data block stores user data for the data write operation and the padding data. The method includes executing, by a memory controller and by the media controller, a data integrity scan on a selected memory page of the specified memory pages of the data block. Execution of the data integrity scan includes re-generating, by the randomizer, the padding data and comparing the re-generated padding data with stored padding data sensed from the selected memory page to identify mismatch data.

Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.

Abstract: Disclosed are methods, systems, and apparatuses for a topology-based dynamic address assignment (DAA) of semiconductor memory devices (e.g., dynamic random access memory (DRAM)). The memory devices may be connected via a daisy chain arrangement that forms a sideband bus. During a DAA process, the topology-based DAA assigns addresses to the memory devices based on their placement on the daisy chain (e.g., their placement within the topology of the sideband bus). The topology-based DAA described herein may facilitate predictably assigning dynamic addresses to memory devices based on, for example, their position on a memory module.

Abstract: Exemplary methods, apparatuses, and systems include a retention latency manager for controlling memory access operations in computing systems based on latency of a set of data bits. The retention latency manager receives a set of data bits from a host. The retention latency manager writes a time stamp. The retention latency manager writes the set of data bits to a location in memory. The retention latency manager computes a time difference between a current time and the time stamp. The retention latency manager selects a set of trim settings using the time difference. The retention latency manager reads the set of data bits from the first location in memory using the set of trim settings.

Abstract: A memory sub-system operable to balance the performance goals of different types of applications. For example, first requests generated by a first type of applications running in a host system to access a storage medium of a memory sub-system can be identified and placed in a first queue. Second requests generated by a second type of applications running in the host system to access the storage medium of the memory sub-system can be identified and placed in a second queue. Servicing to the first queue and the second queue can be interleaved according to the performance requirement (e.g., based on throughput in storage access) of the first type of applications and the performance requirement (e.g., based on latency in storage access) of the second type of applications.