Abstract: Some embodiments of the disclosure provide an apparatus comprising a gate structure on a semiconductor substrate and a layered buffer on the gate structure. The layered buffer includes a first buffer layer including an oxide, and a second buffer layer including for example a nitride under the first buffer layer, capable of preventing ingress of oxygen from the first buffer, oxide layer to the gate structure. In the case of a CMOS device, an NMOS transistor may include a tensor stressor layer on the gate structure. The layered buffer may be provided between the gate structure and the tensor stressor layer.

Abstract: A memory device stores data and stress values in one or more memory arrays. Each time a row in the memory array is accessed, one or more rows near the accessed row experience stress. The stress values represent the stress experienced by the nearby rows. Stress values associated with an accessed row and the rows near the accessed row are read out, adjusted, and stored back in the memory array. A row that is near an accessed row is refreshed when the stress value associated with that row equals or exceeds a threshold.

Abstract: A variety of applications can include memory devices having memory cells, where each memory cell can have an engineered tunnel region between a channel structure of the memory cell and a charge storage region of the memory cell. The engineered tunnel region can be directed to improved read, program, and retention operations of the memory region. In various embodiments, the engineered tunnel region can have multiple dielectric regions with a dielectric constant modulation by inserting material having a dielectric constant that is low relative to silicon nitride and material having a dielectric constant that is high relative to silicon nitride. In various embodiments, the engineered tunnel region of a memory cell can have multiple dielectric regions with material having deep traps near the charge storage region of the memory cell. Other engineered tunnel regions are disclosed.

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first layer of imageable resist is exposed to actinic radiation and developed to form a first opening there-through in the stair-step region. The developed first layer is used in a plurality of alternating etching and lateral-trimming steps that widens the first opening and forms two opposing flights of stairs in the stack in the stair-step region. A second layer of imageable resist is formed directly above the two opposing flights of stairs. The second layer is exposed to actinic radiation and developed to form a second opening there-through. The second opening exposes all of the stairs of one of the two opposing flights.

Abstract: Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.

Abstract: Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.

Abstract: Exemplary methods, apparatuses, and systems write data to a first wordline of a partially programmed block of memory. A second wordline of the block is determined to fail to satisfy a first margin threshold by comparing a first voltage threshold of the second wordline to a reference voltage. In response to the second wordline failing to satisfy the first margin threshold, a second margin test is applied to the block. In response to determining the block passed the second margin test, data is written in a subsequent write operation to the block using an adjusted trim setting.

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Abstract: Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.

Abstract: A decoding operation is performed by receiving a command to read a correction matrix comprising multiple bit-values from memory of a decoder. The decoding operation also includes, responsive to receipt of the command, generating, using circuitry of a decoder, a predetermined correction matrix comprising a same bit-value. The decoding operation further includes providing the predetermined correction matrix to a decision engine to perform the decoding operation.

Abstract: Various aspects of the present disclosure relate to determining data migration priorities in a memory sub-system. A processing device performs a scan operation, such as a read disturb scan, to detect one or more errors in a memory block of the plurality of memory blocks. The processing device determines, based on a result of the scan operation, to perform a data migration operation to move data from one or more memory segments of the memory device to one or more other memory segments of the memory device, wherein the one or more memory segments of the memory device include at least one page of the memory block. The processing logic determines a corresponding priority level of the data migration operation. The processing logic performs the data migration operation based on the corresponding priority level.

Abstract: Methods, systems, and apparatuses include sampling a memory subportion of a portion of memory, where the memory subportion includes multiple wordlines. A sampled voltage value for the memory subportion is determined based on the sampling. A maximum start voltage delta is received for the memory subportion, where the maximum start voltage delta is an estimated difference between the sampled voltage value and a lowest voltage value for the memory subportion. A start voltage to apply during programming of the memory subportion is determined using the sampled voltage value and the maximum start voltage delta.

Abstract: A stacked memory device (e.g., a high-bandwidth memory (HBM) device) having a storage component is disclosed. The stacked memory device can include a first logic die, one or more memory dies, a second logic die, and one or more storage dies. The first logic die is coupled with the one or more memory dies and the second logic die through TSVs. The second logic die is coupled with the one or more storage dies through additional TSVs. The first logic die can issue commands to the one or more memory dies that cause the one or more memory dies to perform operations (e.g., read/write operations). The first logic die can also issue commands to the second logic die that cause the second logic die to issue commands to the one or more storage dies to perform operations.

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

Abstract: A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes moisture impermeable layer. The assembly includes a first substrate and a second substrate electrically connected to a surface of the first substrate. The assembly includes a layer between the two substrates with the moisture impermeable layer between the layer and the surface of the first substrate. The layer may be non-conductive film, die attach film, capillary underfill, or the like. A portion of the surface of the first substrate may include a solder mask between the moisture impermeable layer and the first substrate. The moisture impermeable layer prevents, or at least inhibits, moisture within the first substrate from potentially creating voids in the layer. The moisture impermeably layer may be a polyimide, a polyimide-like material, an epoxy, an epoxy-acrylate, parylene, vinyltriethoxysilane, or combination thereof.

Abstract: Methods, systems, and devices for power envelope modification for memory systems based on time to thermal throttle are described. A memory system may dynamically change the power limit based on operating conditions associated with the memory system. For example, the memory system may measure the time before entering a thermal throttle mode. If the time is relatively short, the memory system may decrease the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to increase. Alternatively, if the time is relatively long, the memory system may increase the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to decrease.

Abstract: Various examples are directed to systems and methods involving a managed NAND non-volatile memory device comprising a memory array and a memory controller. The memory controller may receive a verification request from a requesting device, the verification request comprising an indication of a first portion of the memory array, and a first known check value. The memory controller may apply an operation based at least in part on first data from the first portion of the memory array to generate a calculated check value and determine verification result data based at least in part on the first known check value and the calculated check value.

Abstract: This disclosure is directed to a system for performing read error handling. The system reads a first portion of a memory block from a memory device and skips reading a second portion of the memory block when determining that a read bit error rate (RBER) associated with the second portion of the memory block transgresses an RBER threshold. The system, before initiating error correction operations on the second portion, continues to read additional portions of the memory block after determining that the RBER associated with the second portion of the memory block transgresses the RBER threshold and performs the error correction operations on the second portion using at least the first portion of the memory block and the additional portions of the memory block to correct the second portion of the memory block.

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to detect read errors in one or more memory cells using a plurality of read thresholds. The controller selects, for inspection, a target valley of a plurality of valleys associated with an individual memory component of the set of memory components. The controller reads the target valley using a first read threshold to obtain a first set of data and reads the target valley using a second read threshold to obtain a second set of data. The controller compares the first set of data to the second set of data and performs one or more memory operations on the target valley in response to comparing the first set of data to the second set of data.