Abstract: Apparatuses, systems, and methods for shared codeword in two-pass access operations. The memory may use a read read modify write write (RRMWW) cycle to write data and metadata to the array. Metadata and a data codeword are read out as part of two read access passes and combined into a shared codeword. Error correction is performed on the shared codeword, and then the corrected shared codeword is modified with write data and metadata. Updated parity is generated based on the modified shared codeword and the modified data and updated parity and the metadata are written as two write access passes.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers. The lower stack comprises lower channel-material strings extending through the lower first tiers and the lower second tiers. An upper stack is formed directly above the lower stack. The upper stack comprises vertically-alternating different-composition upper first tiers and upper second tiers. The upper stack comprises upper channel-material strings of select-gate transistors. Individual of the upper channel-material strings are directly electrically coupled to individual of the lower channel-material strings. The upper and lower first tiers are conductive at least in a finished-circuitry construction. The upper and lower second tiers are insulative and comprise insulative material.

Abstract: Methods, systems, and devices for techniques for erasing data in a memory device are provided. The memory device comprises a plurality of memory blocks. Each of the plurality of memory blocks comprises a plurality of word line segments. Each of the plurality of word line segments comprises one or more word lines forming a subset of word lines in the memory block. The memory device further comprises a memory controller configured to perform receiving an erase command for erasing data in the memory block, and in response to receiving the erase command, causing to apply one or more erase pulses to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different time periods such that while data erasing begins at a first word line segment, data erasing does not begin at another word line segment.

Abstract: Memory circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers extending in a memory array region and into a stair-step region. Channel material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The stair step region comprises a cavity comprising a flight of stairs extending along a first direction. Multiple treads in individual of the stairs extend along a second direction Individual of the treads comprise conducting material of one of the conductive tiers. The cavity comprises a pair of laterally-opposing outermost sidewalls that individually extend along the first direction. The multiple treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally opposing outermost sidewalls.

Abstract: A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above insulator material. A mask is used to subtractively etch both the transistor material and thereafter the insulator material to form a plurality of pillars that individually comprise the transistor material and the insulator material. The insulator material is laterally-recessed from opposing lateral sides of individual of the pillars selectively relative to the transistor material of the individual pillars. The individual pillars are formed to comprise a first capacitor electrode that is in void space formed from the laterally recessing. Capacitors are formed that individually comprise the first capacitor electrode of the individual pillars. A capacitor insulator is aside the first capacitor electrode of the individual pillars and a second capacitor electrode is laterally-outward of the capacitor insulator.

Abstract: An example apparatus includes: first and second chip regions arranged in a first direction, each of the first and second chip regions including a plurality of circuit elements; a scribe region arranged between the first and second chip regions in the first direction and extending in a second direction perpendicular to the first direction; and a rectangle-shaped landing pattern having a notch at a substantially center portion in the first direction of each of two sides opposite to each other in the second direction.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. A channel-material string is in individual channel openings in the vertically-alternating first tiers and second tiers. A conductor-material contact is in the individual channel openings directly against the channel material of individual of the channel-material strings. The conductor-material contacts are vertically recessed in the individual channel openings. A conductive via is formed in the individual channel openings directly against the vertically-recessed conductor-material contact in that individual channel opening. Other aspects, including structure independent of method, are disclosed.

Abstract: A memory sub-system, including: a random access memory; a storage medium having a storage capacity accessible to a host system through commands communicated via a plurality of submission queues to the memory sub-system; and a controller. The controller is configured to: retrieve, from a first submission queue among the plurality of submission queues, a first command configured with a first address to access the storage medium; determine, based at least in part on the first command, that a second address configured in a second command following the first command in communication via the first submission queue from the host system to the memory sub-system is predictable; predict a third address according to the first address configured in the first command; and retrieve, from the storage medium and according to the third address, a data chunk into the random access memory, before the second command is retrieved.

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

Abstract: Systems, apparatus, and methods related to configurable data protection circuitry. A memory includes a plurality of memory devices and a memory controller that can be coupled to the memory via a plurality of channels. The channels comprise respective subsets of the plurality of memory devices. The memory controller comprises data protection circuitry to accommodate a first codeword configuration of a number of codewords responsive to the plurality of memory devices having a first operating mode corresponding to a first input/output (I/O) width and accommodate a second codeword configuration of the number of codewords responsive to the plurality of memory devices having a second operating mode corresponding to a second I/O width, as well as switch between the first operating mode of the plurality of memory devices and the second operating mode of the plurality of memory devices.

Abstract: Some embodiments of the disclosure provide an apparatus comprising: a word line array including a plurality of word lines each extending through a memory mat in a first horizontal direction, the plurality of word lines including first and second word lines arranged adjacent to each other in a second horizontal direction; and a word line contact of the first word line, the word line contact separated from the second word line by a gap. The first and second word lines each have a first oxide film at a center area of the word line array in the memory mat. The first and second word lines each have a second oxide film at an edge area of the word line array outside the memory mat, the second oxide film having a thickness greater than a thickness of the first oxide film.

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

Abstract: Methods, systems, and devices for training procedure change determination to detect an attack are described. A host device may perform one or more training procedures to train aspects of a memory device (e.g., a dynamic random-access memory (DRAM) component). A training procedure may depend on a current (e.g., present, within a threshold duration) metric associated with the memory device, such as a current channel metric for a channel between the memory device and the host device. The host device, memory device, or another device, may store a set of reference values associated with a training procedure and may compare a result of a training procedure to a reference value of the set to determine whether the training procedure has changed. If the training procedure or a related value has changed, the memory device may disable one or more features of the memory device to protect against a potential attack.

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

Abstract: Methods, apparatuses, and systems related to conductive structures are described. An example conductive structure includes a first conductive material including a conductive metal nitride, where the first conductive material has a thickness of at least 0.5 nanometers, and a second conductive material including a conductive metal, where the second conductive material is disposed on a first surface of the first conductive material.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a conductive plate, a top electrode in contact with the conductive plate and shared by a plurality of bottom electrodes included in the integrated assembly, a bottom electrode having a top surface, a bottom surface, and an exterior circumferential surface, and a ferroelectric insulator that separates the top electrode from the bottom electrode. In some implementations, a support structure is not present between a top surface of the ferroelectric insulator and a bottom surface of the conductive plate. The integrated assembly may include a leaker device having a top surface, a bottom surface in contact with the top surface of the bottom electrode, and an exterior circumferential surface. The leaker device may be configured to discharge charge from the bottom electrode to the conductive plate.

Abstract: Methods and non-transitory machine-readable media associated with a virtual queue are described. A method can include receiving, by a processing resource, a request from a user to join a virtual queue, adding, by the processing resource, the user to the virtual queue, determining, by the processing resource, a queue optimization based on an estimated wait time for the user in the virtual queue, and providing to the user, by the processing resource, the queue optimization including the estimated wait time for the user in the virtual queue. The virtual queue can be updated in an example.

Abstract: A NAND memory device is modified to include current written page (CWP) and current written block (CWB) variables for each plane. When the CWP and CWB variables are set, the NAND memory device performs an erase page check (EPC) on the indicated page and the previous page. The indicated page should be an empty page, otherwise, when the page is written to, data will be overwritten. The previous page should be a programmed page, otherwise, when the current page is written to, the previous page will be skipped. Page write commands identify the page and block being written to. The NAND memory device compares the page and block of the page write command to the CWP and CWB to confirm that the host system is writing to the correct page.

Abstract: A memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAV constructions that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAV constructions comprise an upper portion directly above and joined with a lower portion. The individual TAV constructions comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method, are disclosed.

Abstract: A memory device comprises a memory array and a memory controller operatively coupled to the memory array. The memory controller includes a processor configured to initiate read operations to the memory array; compare the number of read operations to a predetermined threshold number of read operations; initiate scanning memory pages of a block of memory cells for errors in response to reaching the threshold number of read operations for the block; and iteratively change the threshold number to a new threshold number, perform the new threshold number of read operations on the block of memory cells, and error scan memory pages associated with the last read operation of the new threshold number of read operations.