Abstract: Apparatuses and methods for reducing standby current in memory array access circuits are disclosed. An example apparatus includes a activation voltage supply line and a sense amplifier coupled to the activation voltage supply line. The sense amplifier is configured to be activated by an activation voltage provided on the activation voltage supply line. A read-write circuit is coupled to a pair of local input/output lines and a pair of global input/output lines, and further coupled to the activation voltage supply line. The read-write circuit is configured to drive the pair global input/output lines based on voltages of the pair of local input/output lines when activated for a read operation and further configured to drive the pair of local input/output lines based on voltages of the pair of global input/output lines when activated for a write operation.

Abstract: A method used in forming an array of capacitors comprises forming first walls along a column direction and second walls along a row direction. The first and second walls individually comprise a first material directly above a second material. The first and second materials are of different compositions relative one another. All of the second material is removed from being directly under the first material in the second walls to form beams that are elongated along the row direction and are suspended between immediately-adjacent of the first walls and to leave the second material directly under the first material in the first walls. Third walls are formed along the row direction. The third walls comprise third material that is of different composition from those of the first and second materials. The third material of individual of the third walls circumferentially-covers the beams. Conductive material is grown over the first and second materials selectively relative to the third material.

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stack in the stair-step region comprises a cavity comprising a flight of stairs in a vertical cross-section along a first direction. The first tiers are conductive and the second tiers are insulative in a finished-circuitry construction. An insulating lining is formed in the cavity atop treads of the stairs and laterally-over sidewalls of the cavity that are along the first direction. Individual of the treads comprise conducting material of one of the conductive tiers in the finished-circuitry construction. The insulating lining is thicker in a bottom part of the cavity than over the sidewalls of the cavity that are above the bottom part. Insulative material is formed in the cavity directly above the insulating lining. Conductive vias are formed through the insulative material and the insulating lining.

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells at segmented drains of the select gate transistors. The segmented drains can have conductive fins integrated with the transistor channel structure and extending vertically from a top border of the transistor channel structure, where the conductive fins are separated from each other by non-conductive regions on the top border. The segmented drain can include portions extending downward below the top border. The transistor channel structures can be integrated with the channel structures of the pillars forming the strings of memory cells. Additional devices, systems, and methods are discussed.

Abstract: Memory circuitry comprising strings of memory cells comprises vertically-alternating insulative tiers and conductive tiers that extend from a memory-array region into a stair-step region across an intermediate region that is between the memory-array region and the stair-step region. The insulative tiers and the conductive tiers comprise memory blocks upper portions of which individually comprise sub-blocks. Sub-block trenches are in the upper portions individually between immediately-laterally-adjacent of the sub-blocks. Strings of memory cells in the memory-array region comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks and in the sub-blocks. The sub-block trenches in the memory-array region, in the intermediate region, and in the stair-step region individually have a top.

Abstract: A processing device in a memory sub-system receives a request to write data to the memory device, wherein the memory device is configured to store a first number of bits per memory cell. The processing device obtains a temperature measurement of the memory device. Responsive to determining that the temperature measurement of the memory device satisfies a first operating temperature threshold criterion, the processing device reconfigures the memory device to store a second number of bits per memory cell, wherein the first operating temperature threshold criterion is associated with the first number of bits per memory cell, and wherein the second number of bits per memory cell is less than the first number of bits per memory cell. The processing device performs a write operation to store the data in the memory device using the second number of bits per memory cell.

Abstract: Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which solve the above problems using a global shared region of memory that combines memory segments from multiple CXL devices. Each memory segment is a same size and naturally aligned in its own physical address space. The global shared region is contiguous and naturally aligned in the virtual address space. By organizing this global shared region in this manner, a series of three tables may be used to quickly translate a virtual address in the global shared region to a physical address. This prevents TLB thrashing and improves performance of the computing system.

Abstract: Methods, systems, and devices for redundant array parity information storage are described. A memory system may store parity information associated with data in one or more latches associated with one or more planes before writing the data from the latches to the one or more planes. The parity information may be transferred from the latches to the one or more planes. The memory system may temporarily transfer the parity information from the latches to the planes before completing the write operation in response to initiating a write operation that uses more of the latches, and may transfer the parity information back to the latches after the write operation is completed. The memory system may store, retrieve, and transfer the parity information to or from the latches according to an interleaving scheme associated with different write operations of the memory system.

Abstract: Memory array structures might include a data line, a common source, and a plurality of sub-blocks of memory cells selectively connected to the data line and to the common source. Sub-blocks of memory cells might include memory cells formed to be around channel material structures, and might include isolation of source-side select lines of adjacent sub-blocks of memory cells. Methods are included for forming such memory array structures.

Abstract: Methods, systems, and devices for cache techniques for memory system read commands are described. A memory device of a memory system may reduce latency associated with cache access operations based on receiving a multi-plane command from the memory system. For example, the memory system may transmit an access command that indicates (e.g., using one or more bits, via a prefix associated with the command) that an access operation is for a multi-plane read of the memory device. The memory device may transfer data from a first cache of the memory device to a second cache of the memory device prior to receiving each address indication for the access operation. As such, the memory device may concurrently perform the transfer of the data with the receiving of at least one address indication, thereby reducing latency associated with the access operation and response times of the memory system.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the memory regions and the intermediate region. The panel is laterally between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. The doped-semiconductor-material is at least part of conductive source structures within the memory regions. Insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Insulative liners are along upper regions of the conductive posts. Some embodiments include methods of forming integrated assemblies.

Abstract: A method to enhance images, including: receiving, in an image processing logic circuit in an integrated circuit device, first data representative of an input image; generating, by the image processing logic circuit, input data for an inference logic circuit in the integrated circuit device; generating, by the inference logic circuit, a column of bits from the input data; performing, by the inference logic circuit using memory cells in the integrated circuit device having threshold voltages programmed to represent at least one weight matrix, operations of multiplication and accumulation, via reading concurrently rows of the memory cells selected according to the column of bits; generating, by the inference logic circuit, output data based on results of the operations multiplication and accumulation; and generating, by the image processing logic circuit using the output data, second data representative of an output image enhanced from the input image.

Abstract: A microelectronic device comprises a stack structure, and slot structures vertically extending through the stack structure and dividing the stack structure into block structures. Each of the slot structures individually comprises an insulative liner material vertically extending through the slot structure and contacting sidewalls of the insulative levels and the conductive levels defining the slot structure, and grains of a material in contact with sidewalls of the insulative liner material. The grains of the material comprise first grains spanning an entire width between the sidewalls of the insulative liner material. Related memory devices, electronic systems, and methods are also described.

Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A bitline voltage is determined using the cycle number and the group. The command is executed using the bitline voltage.

Abstract: Methods, systems, and devices for techniques for memory error correction are described. A memory device operates refresh operations and refresh with error correction (ECC) operations independently. For example, the memory device includes an ECC patrol block having an error correction counter which indicates a row on which to perform an error correction procedure. Additionally, the memory device includes a refresh counter which indicates a row on which to perform a refresh operation. In response to receiving a command of a first type, the memory device modifies the error correction counter and maintains the refresh counter. Alternatively, in response to receiving a command of a second type, the memory device modifies the refresh counter and maintain the error correction counter.

Abstract: Methods, systems, and devices for logical-to-physical (L2P) mapping for enhanced granularity data storage are described. A memory system may support write operations according to multiple different write granularities and corresponding data transfer sizes. Entries that map logical addresses to physical addresses within the memory system may include first entries associated with a first data transfer size and second entries associated with a second data transfer size that is greater than the first data transfer size. If the memory system receives a write command that indicates a size of data that is less than or equal to the first data transfer size, the system may update the first entries to indicate a mapping. Data indicated via write commands associated with larger data sizes may be mapped by the second entries. The varying entry structure may support improved write operations and throughput for storage of data at varying granularities.

Abstract: A system for providing usage model context aware power management in secure systems with embedded hardware security modules is disclosed. The system determines a context associated with a transaction with a memory device that is initiated by a host device. Based on the context, the system sets conditions within its internal data structures and state machines. The context may indicate that the transaction is a secure transaction requiring cryptographic services of the memory device. Flags are set in firmware of the memory device indicating a need for context aware power management and for cryptographic services. If a power management function to reduce power to the memory device is to be executed, the firmware rejects the transaction until the memory device reenters a functional mode. If the function is not to be executed, the firmware provides the host with a notification of an impending power state change for the memory device.

Abstract: Methods, systems, and devices for a single plug flow for a memory device are described. In some examples, the memory device may include one or more plugs formed above respective bit line plates. The plugs may include a liner and one or more sacrificial materials that are removed during a subsequent etching operation. Accordingly, pillars may be formed above the plugs, and may be generally aligned with the respective bit line plates.

Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include transistors formed from a plurality of semiconductor fins, and using a number of conductive lines passing through trenches between the fins to serve as a gate for the transistor.