Abstract: An apparatus and method are disclosed that define a new, uniform I/O (input/output) interface architecture between the processor module and the motherboard of a computer system, and between the motherboard and expansion boards, via uniform connectors designed to work with the new architecture, such that many different pin-outs are available to the processor module, the interface being dynamically configurable by component control logic of the processor module. Positioning of supplemental connectors (e.g. for I/O or communications) on edges of the cards defines an unimpeded airflow path allowing for efficient cooling of the system.

Abstract: The present invention provides a method and apparatus for arbitrating master-slave transactions. The apparatus includes a slave device adapted to receive a first request from a first master device. The apparatus further includes a record of one or more previous requests from the first master device and at least one additional master device, wherein the slave device is adapted to grant the first request based upon the record.

Abstract: A method for protecting reliability of data associated with a data array is provided. The method initiates with defining state information associated with the data array. Then, crucial state information is identified from the state information. Next, a copy of the crucial state information is generated. Then, the state information and the copy of the crucial state information are protected. Next, a worst case state associated with non-crucial information is defined. In response to detecting an error associated with the non-crucial information, the method includes defaulting to the worst case state. A computer readable media and a shared memory multiprocessor chip are also provided.

Abstract: A method for quantifying effects of resonance in an integrated circuit's power distribution network is provided. The power distribution network includes a first power supply line and a second power supply line to provide power to the integrated circuit. Test ranges are selected for two test parameters, reference voltage potential of a receiver and data transmission frequency of the integrated circuit. At each combination of the two test parameters, bit patterns are transmitted by the integrated circuit to the receiver. A comparison is made between the transmitted bits and the received bits to determine whether the transmitted bits were correctly received. The comparison may be used to determine and report a range of values for the reference voltage potential and data transmission frequency that allow the transmitted bits to be correctly received.

Abstract: A data imaging system is managed by a three-tiered system. The lowest, or agent, tier comprises Common Information Model (CIM) provider objects that reside in the host providing the data imaging service and can make method calls on low-level kernel routines that implement the service. The middle, or logic, tier is a set of federated Java beans that communicate with each other, with the CIM providers and with the upper tier of the system and provide the business logic for the system. The upper, or presentation, tier of the inventive system comprises web-based presentation programs that can be directly manipulated by management personnel to view and control the system from virtually anywhere in the network.

Abstract: A method and apparatus provides the capability for activating, i.e., annealing or ablating, LASER activated fuses from the back-side of an integrated circuit chip using multiple-photon absorption techniques that allow the absorbed LASER energy to be highly localized in three dimensions. According to the invention, the photons from the LASER have an energy less than the band gap energy of the substrate material, therefore absorption in areas of the substrate other than the focal point is avoided. According to the invention, objects such as LASER activated fuses that lie either within the integrated circuit substrate, or on the opposite surface, i.e., the active surface, of the integrated circuit substrate can be accessed and activated by the LASER energy. Consequently, using the method of the invention, LASER activated fuses can be activated after the integrated circuit chip has been mounted in a flip-chip configuration and/or as part of a Multiple-Chip-Module.

Abstract: A content addressable memory (CAM) device having a cascaded CAM array. The cascaded CAM array includes a first array of CAM cells and a second array of CAM cells. A first plurality of compare signal lines is coupled to the first array CAM cells and a second plurality of compare signal lines coupled to the second array of CAM cells. A plurality of storage elements have inputs coupled to the first plurality of compare signal lines and outputs coupled to the second plurality of compare signal lines.

Abstract: An electronic assembly includes a housing having a first portion and a remaining portion. The first portion includes a surface forming an outer wall of the housing. The electronic assembly also includes a component such as a CD ROM drive, for example, that may be mounted on the first portion of the housing. Further, at least one additional component, such as a motherboard, may be mounted on the remaining portion of the housing. The first portion of the housing is rotatably attached to the remaining portion of the housing. When the first portion of the housing is rotated into a closed position, the component and the additional component are positioned adjacent to each other. However, when the first portion of the housing is rotated into an open position, the component and the additional component are moved away from each other to allow access to the additional component.

Abstract: A graphics system invokes a dicing process if one or more edges of a triangle T have length greater than a maximum length (LMAX), invokes a central subdivision process if a coverage estimate for the triangle T is greater than a maximum coverage and all edges of triangle T have length less than or equal to LMAX, invokes rendering of a sequence of one or more single-layer triangles based on triangle T if the coverage estimate for triangle T is less than or equal to the maximum coverage and all edges have length less than or equal to LMAX. Said invocation of rendering of the sequence of single-layer triangles results in the application of a plurality of texture layers to samples corresponding to triangle T. The samples are stored in the TAB between the application of successive layers of said plurality of texture layers.

Abstract: A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Abstract: A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

Abstract: A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.

Abstract: A mechanism is disclosed for enabling efficient testing of a set of computer code. Untested code portions within a body of code are determined, and testing priorities are assigned to untested code portions according to how frequently the untested code portions are likely to be invoked during normal operation. More frequently invoked untested code portions are ranked higher than less frequently invoked untested code portions. The prioritized data may be used by a testing team to determine which additional tests should be created for effective and efficient testing of the body of code.

Abstract: Techniques are provided for controlling data access to maintain data integrity. A request is received to perform an action on a data element. The request is analyzed based on at least one data access rule associated with the data element. This analysis further utilizes a data structure model associated with the data element. The request is approved if the request satisfies the data access rule. The request is rejected if the request does not satisfy the data access rule.

Abstract: A speech-translating remote control includes a microphone operable to receive speech command, thereby outputting a speech signal; an audio transmitter operably connected to the microphone to transmit an audio input signal to a host system based on the speech signal; a signal receiver to receive a command signal transmitted by the host transmitter; and a signal transmitter operably connected to the signal receiver to transmit a control signal to an appliance based on the command signal.

Abstract: An optical transmitter for transmitting a first output data signal and a second output data signal, the optical transmitter comprising: a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive a first input data signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first input data signal and the second input data signal; a first electro-optical converter, the first electro-optical converter coupled to the latch, the first electro-optical converter operable to transmit the first output data signal; and a second electro-optical converter, the second electro-optical converter coupled to the latch, the second electro-optical converter operable to transmit the second output data signal.

Abstract: Embodiments of a system and method for providing class dependency graph-based class loading and reloading may be used to segregate namespaces in a graph-centric way, and may provide a set of normalized topologies that may be used to efficiently support hot-swapping of programmatic logic such as classes, applets, and beans, among other applications. Embodiments may provide a domain-independent, flexible and robust namespace segregation technique that is based on the dependency between the various classes and not on details like the roles the classes play. The problem of segregating namespaces is formulated as a graph theory problem, and a solution is sought through graph techniques. The graph may be normalized by identifying and grouping interdependent classes and non-interdependent classes in separate groups. A directed dependency relationship of the groups may be determined using the relationships between the member classes of the groups.

Abstract: The present invention is directed toward using patterns in APDU to perform identification data substitution. According to one or more embodiments of the present invention, a user inserts a smart card into a card reader connected to a client computing device. Then, the user enters a PIN. The PIN is embedded into an APDU which is sent to the card reader and is presented to the smart card. The APDU contains special patterns that specify to the card reader where and in what format the PIN should be embedded into a prototype APDU that is constructed in the card reader and presented to the card for verification.

Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: Apparatus forming a computer system or such-like is disclosed that includes a central processing unit (CPU) and a power supply unit. The CPU provides a digital voltage ID (VID) signal output indicative of the power supply voltage that it desires to receive. The power supply unit has a control input for receiving a digital VID signal from the CPU. The power output from the unit is then provided to the CPU at a voltage level in accordance with the received digital VID signal. A VID offset generator is interposed between the CPU and the power supply unit. This receives the digital VID signal from the CPU, and modifies it by applying a positive or negative offset. The modified digital VID signal is then passed to the power supply unit, which supplies a voltage to the CPU as per the modified VID signal, rather than the VID signal originally output by the CPU.