Abstract: Various embodiments of systems and methods for performing write cache mirroring may involve accessing different mapped regions within a memory. The memory controller may automatically mirror write requests to another memory. Write requests targeting one mapped region may be verified such that local completion of the write indicates that the mirrored write has also completed. Write requests targeting another mapped region may be unverified. Unverified writes may be verified by performance of a verified write.

Abstract: Exemplary embodiments of the invention provide a system, method and apparatus for frequency calibration of a free-running, harmonic oscillator. A reference oscillator provides a reference frequency. An exemplary system comprises the harmonic oscillator, a frequency divider, a comparator, and a reactance modulator. The oscillator comprises a plurality of switchable reactance modules and a coefficient register, and provides an oscillation signal having an oscillation frequency. The frequency divider provides an output frequency as a fraction of the oscillation frequency. The comparator compares the output and reference frequencies and provides a comparison signal when the output frequency is not substantially equal to the reference frequency.

Abstract: In various embodiments, the invention provides a frequency controller to control and provide a stable resonant frequency of a clock generator and/or a timing and frequency reference. Such stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted.

Abstract: Various embodiments of systems and methods for implementing filter-based attribute value access control are disclosed. In one embodiment, a method involves designating a location in the directory server, providing attribute related data that includes a filter expression, and selectively controlling access to an entry situated at the designated location using the filter expression in the attribute related data. For example, access to an attribute of the entry may be denied if a criterion defined by the filter expression associated with the attribute is not met by a first value of the attribute.

Abstract: A distributed system provides for separate management of dynamic cluster membership and distributed data. Nodes of the distributed system may include a state manager and a topology manager. A state manager handles data access from the cluster. A topology manager handles changes to the dynamic cluster topology. The topology manager enables operation of the state manager by handling topology changes, such as new nodes to join the cluster and node members to exit the cluster. A topology manager may follow a static topology description when handling cluster topology changes. Data replication and recovery functions may be implemented, for example to provide high availability.

Abstract: Method and apparatus are disclosed that allow boot code within the apparatus to be updated using a system controller. The apparatus includes a central processing unit (CPU) and a programmable memory that contains boot code at a predetermined location for use in booting the CPU. The apparatus further includes a bus and a bus master for the bus. The CPU accesses the boot code via the bus and the bus master. The apparatus further includes a system controller. This is operable to write boot code into the programmable memory over the bus. In one embodiment, the above components form a single subsystem within an array of such subsystems. A single control point for the array can transmit updated boot code to the system controller for loading into the programmable memory. This then provides a single interface for simultaneously updating the boot code in all subsystems.

Abstract: A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.

Abstract: A garbage collector that operates in accordance with the train algorithm designates some cars as “special” cars into each of which at most a single object is allowed. When an object in a car being collected is referred to by a reference located in such a special car, the collector may depart from the conventional evacuation approach of placing the evacuated object into the train containing the reference referring to it. If the reference is located in an object referred to from a train younger than the train in which the reference is located, the referred-to object in the car being collected is not evacuated to the train that contains the reference to it. Instead, it is evacuated to the train from which the object containing that reference is referred to.

Abstract: A video routing system including a plurality of video routers VR(0), VR(1), . . . , VR(NR?1) coupled in a linear series. Each video router in the linear series may successively operate on a digital video stream. Each video router provides a synchronous clock along with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. A common clock signal is distributed to each of the video routers. Each video router buffers the common clock signal to generate an output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream.

Abstract: Mechanisms and techniques provide a system for composing a complex constructs for use on a graphical display of a computerized device. The system receives a selection of basic constructor objects for use in the complex object. The basic constructor objects are chosen from a set of basic constructor object types including a button object type, a dial object type, an edit object type, and a container object type. The systems also receives a selection of one or more personalities to assign to the basic constructor objects. The personalities define extensions to basic constructor object operation and define a view for the object when rendered on an interface. The system combines the personalities and the basic constructor objects to define complex constructs such as menus, a scrollbars and the like. Personalities can be modified to alter the complex construct from one operational state to another.

Abstract: A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the spill instructions without having to determine whether a remaining portion of the spill instructions will execute without exceptions.

Abstract: The present invention provides a method and apparatus for a bandwidth adaptive image compression/decompression scheme. In one embodiment, the present invention uses a special protocol between the sender and the receiver to measure the latency of the connection. This protocol and its result are sent and received at an interval based on a dynamic feedback loop algorithm. Based on the results of the protocol, a compression scheme is chosen. This scheme uses CPU time conservatively, and also transmits the most interesting data first. In another embodiment, the present invention throws away data that is repetitious, especially when the connection is down for a short period of time. In yet another embodiment of the present invention, measurements are taken for the perceptual degradation of the image for various compression schemes, and the results are supplemented with the results of the protocol to choose a viable compression/decompression scheme.

Abstract: A method for identifying a least recently used cache entry in a cache. The method includes receiving a cache access request, determining whether the contents of the main memory address are present in the cache, associating, when the contents of the main memory address are not present in the cache, updating more significant bits of a pseudo least recently used pointer when the contents of the main memory address are not present in the cache, and updating more significant bits and less significant bits of the pseudo least recently used pointer when the contents of the main memory address are present in the cache. The cache access request is associated with a main memory address. The memory address has a set within the cache and the set includes a plurality of ways.

Abstract: Improved techniques for loading class files into virtual computing machines are disclosed. These techniques provide a mechanism that will generally improve the efficiency of virtual machines by selectively loading information into a virtual machine. As will be appreciated, this allows a better use of the resources of the virtual machine. This is especially effective in virtual machines that operate with limited memory resources (e.g., embedded systems). In one embodiment, class files suitable for loading into a virtual machine are initially loaded into a memory portion (e.g., heap memory). Then, information that is needed to be loaded into the virtual machine is selected. Finally, only the selected information is loaded into the virtual machine.

Abstract: A computer arrangement with a processor (5) and at least one memory unit (7, 9, 11, 13) connected to the processor (5) and including dynamic random access memory (13), wherein the computer arrangment is arranged to use but not to refresh at least part of the dynamic random access memory (13) while running a program.

Abstract: In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. The data cache unit has a plurality of storage cell banks. Each storage cell bank has valid bit array unit and a tag unit for each execution unit incorporated therein. Each valid bit array unit has a valid/invalid storage cell associated with each data group stored in the storage cell bank. The valid bit array units have a read/write address port and snoop address port. During a read operation, the associated valid/invalid signal is retrieved to determine whether the data signal group should be processed by the associated execution unit. In a write operation, a valid bit is set in the valid/invalid bit location(s) associated with the storage of a data signal group (or groups) during memory access.

Abstract: The present invention provides a method and apparatus for inter-domain data transfer. The method includes mapping a memory region of a source device into a central device and mapping a memory region of a target device into the central device. The method further includes transferring data from the mapped memory region of the source device to the mapped memory region of the target device.

Abstract: Mechanisms and techniques provide a system that operates in a computerized device to index content. Such a system allows registration of content indexing services and then receives repository content of at least one type. The system identifies a content indexing service associated with the at least one type of repository content from the set of available content indexing services. The system operates the content indexing service on the repository content to produce classification data or metadata derived from the repository content in addition to original classification data. The system then associates the classification data to a registry of classification data to allow indexing access to the repository content based on the classification data. By automatically indexing content, more comprehensive indexing is supported.

Abstract: Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. Such exposure may be advantageously provided in situ by causing the sense amplifier to sense values purposefully skewed toward a predominate value selected to cause the compensating shift. In some realizations, purposefully skewed values (e.g., value and value_1) are introduced directly into the sense amplifier. In some realizations, an on-chip test block is employed to identify and characterize sensing mismatch.

Abstract: Embodiments of the present invention provide methods and apparatuses for accessing MD atomically. For one embodiment, the local cache and the remote cache are each provided with an MBE. To perform an atomic access operation, the local processing system allocates a burst descriptor buffer. The burst descriptor buffer is used to specify the addresses to be atomically accessed. For write operations, the burst descriptor buffer also specifies the update data. The addresses, and data, if any, are then transmitted to the remote cache as a series of packets constituting a single data access request. The MBE of the remote cache then performs the operations contained in the request. Upon completion of all of the operations the remote MBE transmits an acknowledgement. For read operations the remote MBE also transmits the requested data.