Abstract: One embodiment of the present invention provides a system that facilitates implementing multi-mode specification-driven disassembler. During operation, the disassembler receives a machine-code version of a computer program. In order to disassemble a specific machine-code instruction from this machine-code version, the system compares the machine-code instruction against a set of instruction templates for assembly code instructions to identify a set of matching templates. Next, the system selects a matching template from the set of matching templates based on the state of a mode variable, which indicates a specificity mode for the disassembler. The system then disassembles the machine-code instruction using the operand fields defined by the matching template to produce a corresponding assembly code instruction.

Abstract: A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Abstract: A content addressable memory (CAM) device having a range compare function. A boundary value is stored within a plurality of CAM cells within the CAM device. A range compare operation is performed to determine whether a comparand is greater than the boundary value. A result signal is asserted if the comparand is greater than the boundary value.

Abstract: The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool (120) to extract information associated with the inputs/outputs from a netlist. The information includes information associated with circuit devices directly connected to the inputs/outputs, particularly information related to device connectivity and the feature sizes of the device. Once the information is extracted, a capacitance determination element (130) aggregates the feature sizes of all the circuit devices connected to each respective input or output, to obtain aggregate feature sizes for each respective input/output. The aggregate feature size is used in determining the total capacitance of the input/output. The total capacitance thus determined can be provided to a timing analysis tool (140), which uses the total capacitance of each input or output to generate a timing model for the circuit.

Abstract: Resource management for controlling allocation of a resource to competing computer processes is achieved through the use of a joining function. A resource manager is responsive to identification of a thread for a first process requesting allocation of the resource, when the resource is already allocated to a thread for a second process, to establish a joining function to the thread for the second process. The joining function is operable to notify the resource manager on termination of the thread for the second process. The resource manager can therefore be operable in response to termination of the thread for the second process to allocate the resource to the first process. The first and second processes can be call handling processes for telecommunications apparatus where the resource manager provides allocation of a telephony resource, such as a modem or network interface, to the competing call handling applications. A telephony interface and the applications can be implemented in the Java™ language.

Abstract: A method for inserting a prefix, including traversing a trie node block structure to obtain a trie node block in which to insert the prefix, determining whether the trie node block is associated with a hash table, if the trie node block is not associated with a hash table: calculating a set of hash values for a trie node in the trie node block, and populating the hash table using the set of hash values calculated for the trie node, and inserting the prefix in an appropriate location in the hash table using at least one of the set of hash values associated with the trie node.

Abstract: Devices utilize elements carried by a fluid in a microchannel to switch, attenuate, shutter, filter, or phase shift optical signals. In certain embodiments, a microchannel carries a gaseous or liquid slug that interacts with at least a portion of the optical power of an optical signal traveling through a waveguide. The microchannel may form part of the cladding of the waveguide, part of the core and the cladding, or part of the core only. The microchannel may also have ends or may be configured as a loop or continuous channel. The fluid devices may be self-latching or may be semi-latching. The fluid in the microchannel is moved using e.g., e.g., electrocapillarity, differential-pressure electrocapillarity, electrowetting, continuous electrowetting, electrophoresis, electroosmosis, dielectrophoresis, electro-hydrodynamic electrohydrodynamic pumping, magneto-hydrodynamic magnetohydrodynamic pumping, thermocapillarity, thermal expansion, dielectric pumping, and/or variable dielectric pumping.

Abstract: A system and method for providing hot-swap status indication in a computer system having redundant power supplies. In one embodiment a system comprises an electrical subsystem that is powered by a first power supply and second power supply. The system further comprises a hot-swap indicator configured to provide a first user indication to indicate whether the first power supply is hot-swappable depending on whether the first power supply is operating at greater than a predetermined power capacity usage, such as fifty percent. The system may also include a second hot-swap indicator for the second power supply.

Abstract: A “lidless” integrated circuit package includes a support member that is arranged to support at least part of a load placed on the integrated circuit package. The support member has or is connected to a flexible support device that is in supportive contact with the load and that is designed to flex dependent on a position of the support member. The flexible support device substantially ensures that a plane of the surface of the flexible support device and a plane of a surface of a semiconductor die of the integrated circuit package are co-planar, thereby leading to a desirable load distribution within the integrated circuit package.

Abstract: A system and method for the static scheduling of test cases. A static scheduler is used to schedule the entire verification test of an integrated circuit in advance. The static scheduler is used in conjunction with a hardware description language (HDL) circuit design, a virtual test bench, and simulation software. The static scheduler is configured to assign test events to resources, or functional units, of the integrated circuit design. Events for a resource are assigned to available time slots, or cycles. During event scheduling, the static scheduler is configured to ensure that there are no resource conflicts for a given time slot. By scheduling all test events in advance, pitfalls associated with dynamic scheduling may be avoided, such as those associated with the use of semaphores. By avoiding the use of semaphores, complex test scenarios and boundary conditions may be more fully exercised, as resources will not be locked. This may allow a more thorough verification of an integrated circuit design.

Abstract: A technique improves the performance of an integrated circuit design by selectively replacing low Vt transistors with standard Vt transistors. The selection of gates for replacement may be based on a multi-path timing analysis. If a low Vt variant of a gate instance increases a path cycle time as compared to a standard Vt counterpart, the maximum of the path cycle times for all paths that include the low Vt variant and the maximum of the path cycle time for these paths with a standard Vt variant are calculated. If the maximum path cycle time for the path including the low Vt variant is greater than the maximum path cycle time for the path including the standard Vt variant, then that low Vt variant is substituted with a standard Vt variant. Thus, integrated circuit designs prepared in accordance with the invention may exhibit improved cycle times.

Abstract: A half-rail differential driver circuit comprises a differential line pair, a high line and a low line, that are charged to half a first supply voltage, typically VDD, by shorting the high output line to the low output line during the pre-charge phase. The half-rail data lines are then pulled up or down during the evaluation phase. Since, according to the present invention, the switching differentials are only half-rail, the coupling capacitance is reduced by half. In addition, since according to the invention, the half-rail differential driver circuit employs a differential line pair, the return path is confined within the differential line pair, virtually eliminating the loop area and therefore virtually eliminating inductive coupling.

Abstract: One embodiment of the present invention provides a system that operatively couples an integrated circuit with a microstrip transmission line through chip lamination. The system includes a first semiconductor die containing the integrated circuit, and a second semiconductor die containing the microstrip transmission line. Unlike metal lines in the integrated circuit, which have relatively small cross-sections, the microstrip transmission line has a cross-section that is large enough so that signal propagation is governed by inductance and capacitance (LC) instead of resistance and capacitance (RC). The first semiconductor die and the second semiconductor die are laminated together so that the integrated circuit on the first semiconductor die is operatively coupled with the microstrip transmission line in the second semiconductor die.

Abstract: A system for providing service attribute information including a directory server containing a hierarchical data store associating users with service attributes through data inheritance, wherein the hierarchical data store includes an organization level and a role level, and attribute templates defined with respect to services and levels, an application for generating a query to the directory server for a service attribute of a particular user of the application, wherein the directory server, in response to the query, is for using inheritance rules from the hierarchical data store to determine and report a service attribute for the particular user of the application.

Abstract: Improved transposition of a matrix in a computer system may be accomplished while utilizing at most a single permutation vector. This greatly improves the speed and parallelability of the transpose operation. For a standard rectangular matrix having M rows and N columns and a size M×N, first n and q are determined, wherein N=n*q, and wherein M×q represents a block size and wherein N is evenly divisible by p. Then, the matrix is partitioned into n columns of size M×q. Then for each column n, elements are sequentially read within the column row-wise and sequentially written into a cache, then sequentially read from the cache and sequentially written row-wise back into the matrix in a memory in a column of size q×M. A permutation vector may then be applied to the matrix to arrive at the transpose. This method may be modified for special cases, such as square matrices, to further improve efficiency.

Abstract: The present invention provides a method and apparatus for error recovery in a system. The apparatus comprises a directory cache adapted to store at least one entry and a control unit. The control unit is adapted to determine if at least one uncorrectable error exists in the directory cache and to place the directory cache offline in response to determining that the error is uncorrectable. The method comprises detecting an error in data stored in a storage device in the system, and determining if the detected error is correctable. The method further comprises making at least a portion of the storage device unavailable to one or more resources in the system in response to determining that the error is uncorrectable.

Abstract: A method for system management of configuration data used by server or groups of servers. In one embodiment, the present invention is comprised of providing information relative to components of the system being managed. A common language is utilized to express the information. An interface is provided to enable inputting of said information. The interface also enables management of the inputted information. In one embodiment, the information is validated during inputting. The validation of inputted information ensures that the information inputted is compliant with a schema of the information. In one embodiment, the information is comprised of defined tasks that are performed by the components of the system. The information is further comprised of specified configurations relative to the defined tasks. The information further comprises a declared schema for representing the information.

Abstract: A modular computer system may be provided. The modular computer system may comprise a carrier operable removably to receive a plurality of computer system modules therein. A plurality of information processing modules can be removably received in the carrier, each module may have a communications port operable to connect to a communications network internal to the carrier. The modular computer system may also comprise a switch operable to connect to the internal communications network to distribute information messages between the modules and to connect to an external communications network. An information distribution module may be provided removably received in the carrier operable connect to the internal communications network to receive an information message, to perform processing on the message to determine a destination, and to forward the message toward the determined destination via the internal communications network.

Abstract: A multiprocessor computer system to selectively transmit address transactions using a broadcast mode or a point-to-point mode. Either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency. A node is formed by a group of clients which share a common address and data network. The address network determines whether a transaction is conveyed in broadcast mode or point-to-point mode. The address network includes a table with entries which indicate transmission modes corresponding to different regions of the address space within the node. Upon receiving a coherence request transaction, the address network may access the table to determine the transmission mode which corresponds to the received transaction. Network congestion may be monitored and transmission modes adjusted accordingly. When network utilization is high, the number of transactions which are broadcast may be reduced.

Abstract: A garbage collector collects at least a generation of a dynamically allocated heap in increments. In each increment, it identifies references located outside a collection set that refer to objects that belong to the collection set, and it evacuates the objects thus referred to before it reclaims the memory space that the collection set occupies. In some collection increments, references to collection-set objects are located both inside and outside the generation. The collector locates all such references, both those inside the generation and those outside it, before it evacuates any objects in response to any of them. By doing so, it is able to reduce the cost of locating references and evacuating objects.