Abstract: A garbage collector divides the garbage-collected heap into “cards.” It maintains a table containing a card-object table entry for each card. A card's entry contains information from which the collector can determine where any references in the card are located and thereby identify objects that may be reachable. Specifically, although each entry is smaller than a memory address, it has enough possible values to give the relative location of the object in which the associated card begins or to direct the collector to another entry for that information. But the entries are additionally grouped into sequences of contiguous entries that together are large enough to contain a complete address. When every card associated with a entry in a given (address-sized) entry sequence begins in the same object, that entry sequence is together given a value that the collector can recognize as indicating that object's absolute location.

Abstract: Apparatus forming a computer system or such-like is disclosed that includes a central processing unit (CPU) and a power supply unit. The CPU provides a digital voltage ID (VID) signal output indicative of the power supply voltage that it desires to receive. The power supply unit has a control input for receiving a digital VID signal from the CPU. The power output from the unit is then provided to the CPU at a voltage level in accordance with the received digital VID signal. A VID offset generator is interposed between the CPU and the power supply unit. This receives the digital VID signal from the CPU, and modifies it by applying a positive or negative offset. The modified digital VID signal is then passed to the power supply unit, which supplies a voltage to the CPU as per the modified VID signal, rather than the VID signal originally output by the CPU.

Abstract: By maintaining consistency of instruction or operation identification between code prepared for profiling and that prepared using profiling results, efficacy of profile-directed code optimizations can be improved. In particular, profile-directed optimizations based on stall statistics are facilitated in an environment in which correspondence maintained between (i) instructions or operations whose execution performance may be optimized (or which may provide an opportunity for optimization of other instructions or operations) and (ii) particular instructions or operations profiled.

Abstract: A service processor is provided for a computer system that includes a host processor and the service processor. The service processor includes a management interface including a first port forming an external user interface and a second port forming an internal console interface. The service processor is operable to provide system management functions within the computer system. It is also operable to respond to external mode switching commands received via the user interface to operate one of two modes. The first mode is a management mode in which commands received via the user interface are processed by the service processor. The second mode is a console mode in which commands received via the user interface are passed by the service processor to the console interface for processing by the host processor. The service processor can be implemented by a dual-ported microcontroller.

Abstract: A system and method for testing an integrated circuit is provided. The illustrative embodiment provides a scan cell for use with automatic test pattern generation (ATPG). In the scan cell of the illustrative embodiment, a flip-flop is configured as a master storage element and a latch is configured as a slave storage element. During standard operating mode, the flip-flop and the latch operate as standard storage elements in the circuit. During a test mode, the flip-flop and the latch form a shift register for shifting test pattern data through the circuit to identify and detect any faults in the circuit design.

Abstract: A printed circuit board (PCB) having an integrated strain gage. In one embodiment, a PCB includes a component footprint suitable for mounting an electronic component. A strain gage is integrated into the PCB in a location under the component footprint. The strain gage includes at least one electrical conductor that is accessible for resistance measurements.

Abstract: A virtual machine, such as a Java™ virtual machine, is configured to operate as a web server so that users, using a browser, can make general-purpose inquiries into the state of the virtual machine or, in some cases, mutate the state of the VM. A “browsable” VM contains a network traffic worker, such as an HTTP thread, a services library, and a VM operations thread, which is an existing component in most virtual machines. The network traffic worker and the VM operations thread communicate through a request data structure. The VM operations thread generates a reply to the request upon receiving a request data structure from the traffic worker. Such a reply can be in the form of an HTTP response containing HTML or XML pages. These pages are transmitted back to the browser/user by the network traffic worker.

Abstract: Providing a contract between an application server and a resource adapter that allows the application server to manage the lifecycle of the resource adapter. When deploying a resource adapter (or during application server startup), an application server bootstraps a resource adapter instance in an appropriate address space. When a resource adapter is undeployed (or during application server shutdown), the application server notifies the resource adapter instance to stop functioning in order to allow safe unloading. The contract provides a mechanism for an application server to manage the lifecycle of a resource adapter instance, allowing an application server to bootstrap a resource adapter instance during resource adapter deployment or application server startup and to expose some of its useful facilities to the resource adapter instance. It also provides a mechanism to notify the resource adapter instance while it is undeployed or during an orderly shutdown of the application server.

Abstract: A distributed system provides for separate management of dynamic cluster membership and distributed data. Nodes of the distributed system may include a state manager and a topology manager. A state manager handles data access from the cluster. A topology manager handles changes to the dynamic cluster topology. The topology manager enables operation of the state manager by handling topology changes, such as new nodes to join the cluster and node members to exit the cluster. A topology manager may follow a static topology description when handling cluster topology changes. Data replication and recovery functions may be implemented, for example to provide high availability.

Abstract: Described is a scheduling system that provides allocation of system resources of one or more processor sets among groups of processes. Each of the process groups is assigned a fixed number of shares, which is the number that is used to allocate system resources among processes of various process groups within a given processor set. The described fair share scheduler considers each processor set to be a separate virtual computer. Different process sets do not share processes, a particular process must execute on a single processor set. In another embodiment of the invention, each process group could be given a separate number of shares for each processor set. Percentage of the resources of the specific processor set allocated to processes of a process group is calculated as a ratio of the shares of the process group on the processor set to the total number of shares of active process groups operating in that set.

Abstract: A method for routing conductors in an integrated circuit design is disclosed, including the steps of determining the number of sensitive conductors requiring placement into quiet track locations, wherein a quiet track location is defined as any track location immediately adjacent to a stable conductor, determining the number of quiet track locations available in said integrated circuit design, and routing one or more sensitive conductors into one or more quiet track locations.

Abstract: A circuit has been developed that reduces the effective strength of a keeper circuit during an interval in which at least one path of an evaluation circuit is sensitive to a keeper device. The keeper circuit includes a keeper gating device coupled to a keeper device that is responsive to a keeper control. The keeper device is sized to overcome leakage current in the evaluation circuit. In some configurations, the keeper circuit includes a weak keeper device that is minimally sized to overcome noise while the keeper device is effectively disabled. In some configurations, the reduction in effective strength of the keeper circuit occurs before arrival of the fastest signal coupled to a sensitive output path of the evaluation circuit and the effective strength is restored after arrival of the slowest signal coupled to the sensitive output path of the evaluation circuit.

Abstract: Disclosed are novel methods and apparatus for provision of efficient, effective, and/or flexible computer system layout and/or cooling configuration. In accordance with an embodiment of the present invention, a method of cooling a computer system is disclosed. The computer system may include a plurality of heat generating electrical components that require cooling. The method includes: providing at least two cooling fans arranged front to back of the computer system to create a push (inlet) and pull (outlet) airflow to cool the computer system and providing a plurality of temperature sensors located at various locations within the computer system to sense a local temperature.

Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Abstract: Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.

Abstract: Improved techniques for representation of objects in a Java™ programming environment are disclosed. The techniques are highly suitable for representation of Java™ objects inside virtual machines, especially those that operate with limited resources (e.g., embedded systems). A cluster of Java™ object representations is disclosed. Each of the Java™ object representations provide a reference to a Java™ object and a reference to the class associated with the Java™ object. Accordingly, a two-tier representation is provided which allows efficient implementation of applications which need to access information regarding both Java™ objects and classes. As a result, quick access to information regarding Java™ objects can be achieved.

Abstract: This functions maintains two trees: a fast access tree referring to memory blocks of a size most often requested, and a general access tree referring to memory blocks of a size less often requested. After satisfying a request for a memory block, the function adjusts the trees to ensure that the fast access tree refers to memory blocks of the size most often requested. By providing such functionality, the function improves its performance over time through self-adaptation.

Abstract: Error detection using data block mapping is provided. One method includes receiving a write request to write a user data block having a first block size, generating an error detection code for the user data block, appending the error detection code to the user data block to form an extended data block, and mapping the extended data block to a plurality of actual data blocks, each actual data block having a block size equal to the first block size.

Abstract: One embodiment of the present invention provides a system that facilitates identifying expansion cards installed in a computer system. The system operates by first examining a device tree for the computer system to identify nodes within the device tree that are associated with the computer expansion cards. Next, the system obtains a subset of parameters from the device tree that are associated with the computer expansion cards, and then performs a pattern match between the subset of parameters for each card and entries in an information file to identify each computer expansion card.

Abstract: One embodiment of the present invention provides a system that facilitates implementing multi-mode specification-driven disassembler. During operation, the disassembler receives a machine-code version of a computer program. In order to disassemble a specific machine-code instruction from this machine-code version, the system compares the machine-code instruction against a set of instruction templates for assembly code instructions to identify a set of matching templates. Next, the system selects a matching template from the set of matching templates based on the state of a mode variable, which indicates a specificity mode for the disassembler. The system then disassembles the machine-code instruction using the operand fields defined by the matching template to produce a corresponding assembly code instruction.