Abstract: An imaging apparatus includes: a light source section (2, 40) including a light source having a wavelength of a plurality of bands; an imaging section (15) configured to convert measurement light source light images of the plurality of bands from the light source section into a plurality of electrical measurement imaging signals, the measurement light source light images being reflected from a surface and an inside of the subject; a calculation section (13, 16, 19) configured to measure a shape of the surface and a shape of the inside in the subject based on the plurality of electrical measurement imaging signals obtained through the conversion in the imaging section; and a composition processing section (19) configured to composition-process the shape of the surface and the shape of the inside measured by the calculation section to create two-dimensional image data or three-dimensional image data about the subject.

Abstract: There is provided: first to fourth magnetic pole yokes 13-16 magnetized by the magnets 11, 12 having both poles on these opposite faces to establish a magnetic pole; and a vibrating membrane 17 disposed between the magnets 11, 12 and electromagnetically coupled to the yokes 13-16 by energizing a meandering coil pattern 17b thereon to vibrate in a predetermined direction. The yokes 13-16 include: abutting sections 13a-16a to be magnetized with abutting against the magnets 11, 12, and magnetic pole sections 13b-16b establishing the magnetic pole in a band shape. The sections 13b-16b each are disposed on the upper and lower sides of the vibrating membrane 17, and disposed with a gap (sound emitting hole 19) such that the magnetic poles different in magnetic polarity are positioned alternately in the lateral direction of the membrane 17 to form magnetic pole faces on the upper and lower sides thereof.

Abstract: Two layers of a plurality of rod-like permanent magnets each having a width Wm, a thickness Tm and a predetermined length are aligned on a plane in such a way that they have opposite magnetic pole orientations alternately and are aligned at a fixed pole pitch ?p are arranged to be opposed to each other with the magnetic pole orientation of each magnet in one of the layers being identical to that of the opposing magnet in the other layer. The opposing surfaces of the magnets are spaced a distance 2×lg from each other, and a vibrating membrane on which coils each having a conductive pattern are arranged is placed in a gap between any two adjacent rod-like permanent magnets in each of the two layers, where lg is a distance from the vibrating membrane to the surface of a magnet. The arrangement of the rod-like permanent magnets is optimized by using Wm, Tm, ?p, and lg.

Abstract: A high impedance can be maintained at a back gate of a MOS transistor constituting a CMOS integrated circuit when power is not supplied, and is switched to an impedance lower than the impedance in use of the CMOS integrated circuit by a switch driven by a power supply of the CMOS integrated circuit. Thus, it is possible to prevent surge breakdown and electrostatic breakdown, and to prevent occurrence of latch up breakdown.

Abstract: A high impedance can be maintained at a back gate of a MOS transistor constituting a CMOS integrated circuit when power is not supplied, and is switched to an impedance lower than the impedance in use of the CMOS integrated circuit by a switch driven by a power supply of the CMOS integrated circuit. Thus, it is possible to prevent surge breakdown and electrostatic breakdown, and to prevent occurrence of latch up breakdown.

Abstract: A phase locked loop (PLL) frequency synthesizer has a phase comparator, a voltage-controlled oscillator, a charge pump circuit, a loop filter, a variable frequency divider periodically changing a division value in response to a frequency division value changing circuit, and a charge pump bias circuit for supplying a modulated reference bias current, for canceling a phase error, to the charge pump circuit. As a result, without generating additional spurious components, conventionally-generated spurious components can be suppressed.

Abstract: It is an object to obtain a nonvolatile semiconductor storage device and a data erasing method thereof in which a time required for a data erasing operation can be shortened. When second and succeeding erasing commands are input at a step SP101, a final voltage value of a batch writing pulse in a last data erasing operation is read from a storage portion (2a) at a step SP102. At a step SP103, next, a control portion (2) sets a starting voltage value of a batch writing pulse in a present data erasing operation based on the final voltage value of the batch writing pulse in the last data erasing operation. For example, in the case in which the final voltage value of the batch writing pulse in the last data erasing operation is VWL=8.00 V and VWell=VSL=−6.00 V, the starting voltage value of the batch writing pulse is currently set to VWL=7.75 V and VWell=VSL=−5.75 V with a reduction of one step.

Abstract: In a signal detection circuit for an optical disk, a comparator converts an analog HF signal into a digital HF signal by using a slice level. A dropout detection circuit detects a dropout of the digital HF signal. A charge-pump circuit feeds back a slice-level control voltage to the comparator based on a result of the detection by the dropout detection circuit. A voltage follower holds and outputs a voltage stored in the capacitor. A switch is turned OFF when a dropout signal has been detected, and outputs to the voltage follower the voltage that has been stored in the capacitor during an ON state of the switch. A second switch is turned ON when a dropout signal has been detected, and applies an output of the voltage follower to the comparator.

Abstract: In a magnetic recording writing circuit, a current having a higher level than a write current is supplied for a period of time during rise and fall of the write current, and a current having a lower level than the write current is supplied for a period of time during overshoot at the rise and fall of the write current. Accordingly, the write current can recover quickly from overshoot.

Abstract: A memory system that generates a reference voltage unaffected by supply voltage variations and is suitable for performing burn-in test is attainable by employing the following configuration. For example, in an MRAM containing a TMR element (Rij) and an N channel MOS transistor (Mij), as memory element, there is disposed a switching circuit (SW1) capable of switching between the state of applying a reference voltage (VrefN) to a memory element and the state of applying a reference voltage (VrefB) for burn-in test having a larger value than the reference voltage (VrefN) to the memory element. At the time of burn-in test, instead of the reference voltage (VrefN) for normal read operation, the reference voltage (VrefB) for burn-in test can be applied via a sense circuit (SC) to the memory element, by applying mode change signals (MODE1 to MODEn) from the exterior and operating the switching circuit (SW1) via a decode circuit (TD).

Abstract: Oscillation outputs which are different for respective detector signals output from a first detector circuit and a second detector circuit, are obtained from a first ring oscillator and a second ring oscillator respectively corresponding to the detector circuits. A selector selects and outputs one of the oscillation outputs. Accordingly, it is sufficient to provide only one pump circuit in a circuit producing a substrate bias voltage.

Abstract: A memory system that generates a reference voltage unaffected by supply voltage variations and is suitable for performing burn-in test is attainable by employing the following configuration. For example, in an MRAM containing a TMR element (Rij) and an N channel MOS transistor (Mij), as memory element, there is disposed a switching circuit (SW1) capable of switching between the state of applying a reference voltage (VrefN) to a memory element and the state of applying a reference voltage (VrefB) for burn-in test having a larger value than the reference voltage (VrefN) to the memory element. At the time of burn-in test, instead of the reference voltage (VrefN) for normal read operation, the reference voltage (VrefB) for burn-in test can be applied via a sense circuit (SC) to the memory element, by applying mode change signals (MODE1 to MODEn) from the exterior and operating the switching circuit (SW1) via a decode circuit (TD).

Abstract: A circuit for amplifying and outputting a pulse width modulated (PWM) signal corresponding to an input audio signal with at least one output transistor and at least one protection control circuit. The protection control circuit compares a detected voltage and a threshold voltage. The detection voltage is a potential difference between a source and a drain of the output transistor. When the detection voltage exceeds the threshold voltage, the protection control circuit outputs a short circuit detection signal to the gate of the output transistor. As a result, the output transistor is turned OFF.

Abstract: An exercise therapy device enables a physically handicapped or aged person to smoothly and continuously perform a pedaling exercise according to the level of his physical strength without overextending himself or herself when he or she undergoes an exercise therapy, to thereby recover his or her exercise function and maintain his or her physical strength. The device is simple in construction, compact in size, light in weight, and can be manufactured at low cost by using only a single actuator which acts as both a load device and an assisting force generating device. The device comprises a drive portion adapted to be manually moved by an exerciser, an actuator connected to the drive portion through a power transmission mechanism, and a control unit for causing the actuator to operate as a load device for providing a load to the drive portion and as an assisting device for providing an assisting force to the drive portion when the drive portion is manually moved by the exerciser.

Abstract: The front surface (where a bonding electrode is located) of a first semiconductor chip 1a is bonded to a die-pad portion of a lead frame by an adhesive 4. The rear surface of the second semiconductor chip 1b is bonded to the rear surface of the first semiconductor chip 1a. The surface electrode of the first semiconductor chip 1a is electrically connected to an inner lead portion 3 of the lead frame by a bonding wire. The surface electrode of the second semiconductor chip 1b is connected to the inner lead potion 3 of the lead frame by the bonding wire.

Abstract: A transistor having a longer channel length and serving as a reference, and a transistor having a shorter channel length and to be subjected to effective channel length extraction are prepared (step ST1.1). A hypothetical point at which a change in a total drain-to-source resistance is estimated to be approximately zero when a gate overdrive is slightly changed is extracted in a mask channel length versus total drain-to-source resistance plane. The values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length and the rate of change in a mask channel length at the hypothetical points (step ST1.6). A true threshold voltage of the transistor having the shorter channel length is determined by a shift amount (&dgr;) which minimizes the standard deviation of the function (F) determined in the step ST1.7 (step ST1.10).

Abstract: A semiconductor manufacturing apparatus and a method of manufacturing a semiconductor device are provided. A horizontal driver (111) and a vertical driver (112) are controlled to move a punch holder (110), or an end portion (101T1) of a punch (101), within a plane defined by first and second directions (D1, D2). A tip (101A) of the punch (101) is brought into contact with leads (11), with a punch-side forming surface (101S) and a die-side forming surface (151S) maintained in parallel relationship. A pressurizer (131) is controlled to move the end portion (101T1) in a fourth direction (D4) toward the die-side forming surface (151S), and the punch-side forming surface (101S) and the die-side forming surface (151S) hold the leads (11) therebetween. A pressure detector (121) detects a load placed upon the punch (101).

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: A strap-like layered resin film (4) having the same width as a semiconductor chip (2) is cut out from a layered resin film (4F) and pressurized while being heated to the temperature below the transition temperature of a resin ribbon (4b), to be bonded onto a predetermined region (1R) of a lead frame (1). Subsequently, removing a cover ribbon (4a) of non-stickiness from the film (4), the semiconductor chip (2) is bonded to the predetermined region (1R) with the resin ribbon (4b) of stickiness heated to about the transition temperature, and further pressurized. With this structure, in bonding the lead frame and the semiconductor chip with the resin film as a bonding material, it is possible to prevent emergence of a void caused by sucking air and extending-off of the bonding material.