Abstract: A device and method for positioning a resin-sealed lead frame that includes semiconductor devices and resin for sealing the semiconductor devices on the lead frame. A break unit is provided for moving the resin-sealed lead frame to a break table. The break unit includes a vacuum suction portion to hold the resin-sealed lead frame during movement and to release it when the resin-sealed lead frame is brought into a receiving opening associated with the break table. The receiving opening is defined by a plurality of guides with the outer tip portions of the guides providing the receiving opening as a space larger than that occupied by the outer configuration of the resin-sealed lead frame. The guides have a slope to position the resin-sealed lead frame onto the break table after it is released in the receiving opening. The break unit further includes push down pins for pushing down and breaking off unwanted extra portions of resin from beneath the resin-sealed lead frame.

Abstract: Each of element processors arranged in correspondence to pixels of a template block and a search window block respectively includes an A register and a B register provided in parallel with each other for storing search window block pixel data respectively, and a T register for storing template block pixel data. Motion vector evaluation value calculation is performed through a first one of the A and B registers and the pixel data stored in the T register, while operated data is transferred to the second one of the A and B registers from the first one of the A and B registers in parallel with the calculation operation, for storing head search window block pixel data of a next search window. A motion vector is detected at a high speed in excellent coding efficiency.

Abstract: A circuit for driving a three-phase brushless DC motor (301) includes a neutral point feedback circuit (201) which operates a three-phase output circuit (202) so that a neutral point potential (V.sub.C) of the motor (301) is maintained at a predetermined potential, and a neutral point potential comparison circuit (500) which determines whether or not the neutral point potential (V.sub.C) is between reference potentials (V.sub.ref1, V.sub.ref2). If the neutral point potential (V.sub.C) is not between the reference potentials (V.sub.ref1, V.sub.ref2), a switch shutoff signal (SC) is activated to turn off a switch (106), so that a current (I.sub.C) is not provided to the neutral point feedback circuit (201). Accordingly, the neutral point feedback circuit (201) stops flowing currents (I.sub.A, I.sub.B) to the three-phase output circuit (202) which in turn stops driving the motor (301). The circuit for driving the motor (301) is prevented from being broken down if a short circuit occurs in the motor (301).

Abstract: A memory which solves a problem of a conventional memory in that it was difficult for the conventional memory to shorten the fall time of its output signal without increasing its size. The number of paths is increased for discharging each of read bit lines by connecting to each of the read bit lines one or more additional transistors for discharging the read bit line, and by utilizing the transistors associated with other read bit line or lines to discharge the particular read bit line. The additional transistors can be provided between the existing transistors. This makes it possible to shorten the discharge time without increasing the size of the memory.

Abstract: Data supplied to a particular data input/output terminal is selected and the selected data is subjected to logic change for each memory cell based on mode setting data from a changing mode setting circuit and is simultaneously written into memory cells simultaneously selected in a memory array. After a reading logic changing circuit changes the data of these simultaneously selected memory cells in the same manner as the writing logic changing circuit does, a coincidence/non-coincidence among the logics of these data is determined, and a signal representing a logic in coincidence is output if a coincidence is found. Thus, testing can be achieved at a high speed and accurately, using test data having various patterns, without increasing the number of data input/output terminals used in the testing operation.

Abstract: In a differential amplifier, when an output node of an output buffer circuit is short-circuited to a high potential supply node, the difference between the potential at an output node of an amplifying circuit and the potential at the output node of the buffer circuit becomes so great as not to be produced in normal operation. A short-circuit protection circuit detects such a state and interrupts or limits a base current supplied to an output transistor of an output pull signal generating circuit, suppressing the flow of excess current into the output node of the buffer circuit.

Abstract: A synchronous semiconductor memory device can achieve either of a pipelined mode and a prefetch mode with one chip. In accordance with CAS (column address strobe) latency 4 instructing signal MCL4 stored in a mode register, a sequence of generation of control signals from a control signal generating circuit is set to either the pipelined mode or the prefetch mode. A mode switching circuit merely switches reset timings of a write buffer in accordance with a CAS latency. Therefore, the internal data write mode can be easily switched in accordance with an operation environment, and the synchronous semiconductor memory device can implement multiple data write modes with one chip.

Abstract: The present invention provides a position control unit having a torque command computing device (a position control circuit, and a speed control circuit) for outputting a torque command signal (q-axis current command signal Iq*) according to a positional command signal .theta.m* given from the outside and a positional detection signal .theta.m for an electric motor, and a torque control device (current control circuit) for controlling a torque of the electric motor according to a torque command signal outputted from the torque command computing device, in which the torque control device selects a gain Kqp or a gain Kqi according to whether an absolute value of a positional deviation between the positional command signal .theta.m* and the positional detection signal .theta.m is larger or smaller than a gain switching reference value P for a positional deviation.

Abstract: A method of controlling an analog-to-digital (A/D) converter for converting an input voltage into digital data. The conversion process includes charging a capacitor with the input voltage to be converted into a digital data, and disconnecting the input voltage from the capacitor. A reference voltage, generated according to digital data, is furnished by a control circuit to a digital-to-analog (D/A) converting unit. The reference voltage is applied to the capacitor by turning on a switch connected between the D/A converting unit and the capacitor. New digital data to be furnished by the control circuit is determined according to a charged voltage on the capacitor. The D/A converting unit causes the reference voltage to be delivered to the capacitor to change to a new value according to the new digital data from the control circuit.

Abstract: A sensorless brushless motor driving circuit for a motor having three phases includes a position detecting circuit for detecting the position of the rotor from the terminal voltages of the motor, a commutation switching circuit for generating commutation switching signals based on a position signal from the position detecting circuit, a motor driving transistor circuit for supplying a motor driving currents to the motor in response to driving signals, a buffer circuit for supplying the driving signals according to the commutation switching signals, and a neutral feedback amplifier for detecting a neutral potential of terminal voltages of the motor, comparing the neutral potential with a reference voltage, outputting a first output to the buffer circuit when the neutral potential of the terminal voltages of the motor is higher than the reference voltage and outputting a second output to the buffer circuit when the neutral potential of the terminal voltages of the motor is lower than the reference voltage.

Abstract: A switching signal generator outputs a switching signal which indicates either an accelerating mode or a decelerating mode by comparing a motor control signal and reference voltage. A first activation signal generator and a second activation signal generator output a first activation signal and a second activation signal, respectively, according to the switching signal from the switching signal generator. A switching control signal generator outputs either a switching control signal based on a motor location signal or a desired electric potential according to the switching signal from switching signal generator, a first activation signal from the first activation signal generator and a motor location signal.

Abstract: A current bypass circuit used in a semiconductor integrated circuit supplied with power from power sources having respective different DC voltages in relation to a reference potential, a p type (or n type) substrate of the semiconductor integrated circuit being connected to the reference potential, includes a current switching circuit and a voltage level detecting circuit. The current switching circuit is connected between the reference potential and the DC voltage source for switching between a conductive state and a cutoff state. The voltage level detecting circuit is connected to a control power source that maintains the current switching circuit in a conductive state when the voltage appearing across both terminals of the current switching circuit is equal or lower than a predetermined voltage. The voltage level detecting circuit cuts-off the current switching circuit when the voltage across both terminals of the current switching circuit exceeds a predetermined value.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: An internal control signal generating circuit produces first and second control signals according to input signals received from a /RAS pin, a first /CAS pin, and a second /CAS pin. Upon readout operation, readout data of first or second memory block is output from a first external terminal while readout data of third or fourth memory block is output from a second external terminal according to the first and second control signals. Meanwhile, upon write operation, input data from the first external terminal becomes write data of first or second memory block while input data from the second external terminal becomes write data of third or fourth memory block according to first and second control signals. Accordingly, it is possible to suppress increase in the chip area caused from increase in number of memory blocks.

Abstract: A motor control apparatus which comprises: a central processing unit which executes general control of processing of the motor control apparatus, a timer portion which generates predetermined pulses from a reference clock signal, a plurality of registers provided corresponding to control signals of respective phases in which data can be reloaded by the central processing unit, shift registers which are able to store the data having the same number of bits as the number of the registers and the values of plurality of registers can be reloaded to the shift registers by the predetermined pulses output from the timer portion, and a control signal generator means which generates control signals of respective phases of a polyphase motor.

Abstract: The access time required to read data from a synchronous memory device is shortened. Drivers (31) drive sub-word lines (30) connected to the gates of pass transistors in memory cells (1). An address decoder (34) selectively activates main word lines (32) prior to the falling of a clock (T). The drivers (31) having a first input terminal connected to the activated main word line (32) activate the main word line (32) at the time when the clock (T) at their second input terminal falls.

Abstract: A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.

Abstract: A power supply unit for a discharge machining apparatus which eliminates overshooting in current rise and improves the electrode consumption characteristics by preventing an operational amplifier as well as a current control element from being saturated, thereby eliminating overshooting during the rise time of the machining current, by clamping the output voltage of the operational amplifier during the stand-by time for electric discharge. The output is clamped by a plurality of resistors and diodes to a state where the output voltage is higher than a power-supply voltage (the output clamp level is set by a resistor). Namely, during the stand-by time when inverted amplification (feedback) via a resistor in an operational amplifier is being carried out, a constant state of feedback is maintained by the diodes.

Abstract: A color CRT device having a cathode ray tube and a deflection coil. The cathode ray tube includes a panel provided with a phosphor surface which has a diagonal diameter of 45 cm or more and has an aspect ratio greater than 4/3 and an electron gun having a high-voltage electrode and a focusing electrode which is disposed in proximity to the high-voltage electrode across a gap. The deflection yoke includes a core which cross-section perpendicular to a tube axis of the cathode ray tube is approximately annular; a saddle type first deflection coil for deflecting in a horizontal direction an electron beam, and a toroidal type second deflection coil for deflecting in a vertical direction the electron beam. The color CRT device satisfies a following relational expression: ##EQU1## where L mm denotes a distance between a central position of the gap and an end surface of the core on a side of the stem,D mm denotes an inner diameter of the core on the side of the stem,.theta.

Abstract: A signal processing device for optical pick-up includes an information signal silicon photo diode (SPD) group having a plurality of silicon photo diodes. A first electrode of each of the respective silicon photo diodes is connected to a common connection node. A second electrode of each of the respective silicon photo diodes is connected to a corresponding electric potential. An information signal amplifier includes an input node connected to the common connection point and an output node for outputting an information signal. A focus signal SPD group includes a plurality of silicon photo diodes. First electrodes of each of the respective silicon photo diodes of the focus signal SPD group are connected in common and further are connected to the input node of the information signal amplifier.