Abstract: An external power source voltage Vcc rises until it exceeds the threshold voltage Vth of an NMOS transistor diode-connected between the external power source (voltage Vcc) and an internal boosted power source (voltage Vpp), whereupon the NMOS transistor is turned on, supplying the internal boosted power source with a voltage (Vcc-Vth) until the power source voltage Vcc reaches its final value. And when the internal reset signal ZPOR expires, the internal boosted power source generating circuit is started to operate so that the internal boost source voltage Vpp is boosted to an intended level Vpp. As a result, when the power is turned on, early stabilization of the boosted power source voltage is realized in a semiconductor storage device.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: A loudspeaker mounting apparatus has a configuration in which frame-parts each having a groove for fitting with a flange of a loudspeaker to be mounted are hinged at one end. By connecting the other ends of the frame-parts, the loudspeaker is fixed on the loudspeaker mounting apparatus and can be mounted at a position.

Abstract: An absolute encoder which is operative to provide a plurality of signals indicating a current position, that signal including a least significant bit whose edge is detected and used as a basis for adjusting the current value under a variety of circumstances, typically based on the speed of the encoder. If the encoder is operating at high speed, a predetermined value may be assigned to the current position, while if operating at low speed, the value may be edge settable at least once at speeds below a limit value.

Abstract: It is an object to obtain a press apparatus and a press controlling method which apply press working to a processed object with accurate press load and is capable of press working with accurate press load without affected by variations in thickness of the processed objects and variations in shut height of molds. A servo motor (51) is connected concentrically to a rotation transmitter (52), and a screw shaft (53) is provided passing through the center of the rotation transmitter (52). The driving force of the servo motor (51) is converted into a thrusting force of a press ram (54) by combining the rotation transmitter (52) and the screw shaft (53). Correct press load is applied to the processed objects and troubles in the press processing caused by variations in thickness of the processed objects can be prevented.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: A current control circuit of a ring oscillator is provided for use in the PLL oscillators.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: y memory blocks are connected in series. A row select signal is output to each memory block from a row address pointer corresponding to a plurality of memory circuits in one memory block. Similarly, a column select signal is output to each memory block from a column address pointer corresponding to a plurality of memory circuits in one memory block. Therefore, the same row and column select signals are applied to each memory block, whereby data is sequentially input/output for every memory block. Thus, the circuit complexity of the row and column address pointers can be reduced.

Abstract: A semiconductor memory device includes a memory cell array (1) having a plurality of memory cells arranged in rows and columns, a plurality of column select lines (3) extending over the memory cell array and coupled to received column select signals generated by a column decoder (100), a plurality of power supply lines (4) provided in parallel with the column select lines to transfer a power supply voltage from a main power supply line (130), and a plurality of ground lines (5) provided in parallel with the column select lines to transfer a ground voltage from a main ground line. A plurality of fuse elements (6) are provided for each of the column select lines. When a short-circuit is found between a column select line and power supply line or a ground line, a fuse element corresponding to the short-circuited column select line is blown off and the short-circuited column select line is isolated from the column decoder.

Abstract: In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells.

Abstract: A magnetic coil, a magnetic contactor using the magnetic coil and a method for manufacturing the magnetic coil are disclosed wherein the magnetic coil does not need increased winding space and can be configured as having two coil terminals protruding in only one direction or as having three coil terminals. A three terminal-type magnetic contactor which uses the magnetic coil does not require an increased amount of space for the winding process, and the size of the three terminal version is reduced while still meeting insulation requirements. The magnetic coil maintains reliable electrical connection even when subjected to mechanical vibration.

Abstract: A current-voltage conversion circuit which is capable of performing logarithmic compression is obtained using only CMOS processes. An emitter of a PNP transistor (10) and a current input terminal (51) are connected commonly to a reverse input terminal of an operational amplifier (53), while a first reference voltage input terminal is connected to a non-reverse input terminal of the operational amplifier (53). A collector of the PNP transistor (10) is grounded and a base of the PNP transistor (10) is connected to an output terminal of the operational amplifier (53) and an output terminal (55). A current (I) is supplied to the current input terminal (51) while a first reference voltage (V.sub.REF1) is applied to the first reference voltage input terminal. The PNP transistor (10) is formed by CMOS processes. The current-voltage conversion circuit is manufactured in a shorter manufacturing time and at a reduced cost.

Abstract: A transmission system comprising a plurality of stations, each having transmission and receiving circuits, that are connected in a ring configuration and use a HDLC-type protocol for transmission. The fault of a transmission circuit in a station can be detected in an idle state time by transmitting a fixed bit pattern during an idle state of transmission. Each station has a fixed bit pattern generator for outputting a fixed bit pattern during an idle time. Each station also has fault detection means which detects a fault when it receives a signal other than transmission data and the fixed bit pattern. Since the state of a line can always be monitored, a fault of the line state can be rapidly identified. Since transmission data is not encoded, the data transmission can be conducted at a high speed.

Abstract: A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.

Abstract: A programmable controller has a programmable controller unit and a peripheral device which facilitates defining and managing set values of both the internal devices of the programmable controller and the upper and lower limit values by allowing the programmable controller unit and the peripheral device to store set values as reference values for judging the magnitudes of current values of information and updating these values under the control of a sequence program. Further, the programmable controller and peripheral device facilitate the consecutive display, real-time display, etc. of the contents of internal devices by displaying sequentially the contents of these internal devices at predetermined intervals under the control of a sequence program. Additionally this invention allows numerically represented character information stored in internal devices of a programmable controller to be displayed in the form of characters by a simple peripheral device.

Abstract: A counter counts clock signals. When a count thereof coincides with the number of rows or columns in a memory cell array, a row or column count coincidence signal is generated and applied to a shift input of a row or column address pointer formed of shift registers. The row or column address pointer is responsive to the clock signals to sequentially shift the count coincidence signal applied to the shift input, so that row or column selecting lines in the memory cell array are sequentially set in the selected state. Since the outputs at final stages in the row and column address pointers are not fed back to the inputs at the first stage thereof, signal delay in a feed back path is not caused, and thus operations for selecting rows and columns are performed at high speed. Also, respective shift register stages in the row and column address pointers have the same construction, and thus regularity thereof is maintained.

Abstract: The apparatus includes a standards conversion circuit for converting a video signal of MUSE standard having an aspect ratio of 16:9 to be applied to an input terminal into a video signal of NTSC standard having an aspect ratio of 4:3 so that no drop out of the video image is generated and no empty space is generated in the video image and outputting the resultant signal through an output terminal. The video signal output from standards conversion circuit includes a deformation of the image originated from the difference in the aspect ratios.