Abstract: It is an object to realize a synchronization circuit with small size and low consumption power which enables capturing and phasing of external data without running external clock in parallel. Internal clock (2) is delayed by a delay line (1) to produce delay clocks (3), and one of the delay clocks (3) having its rise almost corresponding to that of an external data signal (6) becomes a select clock (5). An elastic store circuit (7) is a circuit which controls a row of D-latches with a row of C elements. Thus the elastic store circuit (7) captures the external data signal (6) with enough set up hold time at timing of the select clock (5) and then outputs the captured external data as an internal data signal (8) in synchronization with the internal clock (2).

Abstract: A k-bit data input and a 1-bit scan input of a scan flip-flop (21.sub.i) of a multiply-accumulation operation unit (4.sub.i) respectively receive a k-bit data output and a 1-bit scan output of a scan flip-flop (21.sub.i-1) of a multiply-accumulation operation unit (4.sub.j-1) in the previous stage. A j-bit data input and a 1-bit scan input of a scan flip-flop (22.sub.i) respectively receive a j-bit data output of an adder (3.sub.i-1) of a multiply-accumulation operation unit (4.sub.i-1)) in the previous stage and a 1-bit scan output of a scan flip-flop (22.sub.j+1) in the next stage.

Abstract: A lateral transistor includes a first conductivity type semiconductor substrate, a first second conductivity type region in the substrate, a second second conductivity type region in the substrate spaced from and partially surrounding the first region including a plurality of sides and corners; an electrically insulating film covering the semiconductor substrate and including respective penetrating holes extending to the first and second regions; a first metal film disposed on the insulating film and contacting the second region through a first of the penetrating holes; and a second metal film disposed on the insulating film and contacting the first region through a second of the penetrating holes wherein the first metal film is missing opposite a first of the corners of the second region and the second metal film extends across the second region at the first corner.

Abstract: A semiconductor integrated circuit device for driving a motor and including a p-type semiconductor substrate having spaced apart first and second areas; power transistors in the semiconductor substrate within the first area; a small signal system circuit in the semiconductor substrate within the second area; and an n-type isolating region in the semiconductor substrate separated from the first and second areas and disposed at least partially between the first and second areas, the n-type isolating region being connected to ground.

Abstract: A first interconnection frame is provided on a semiconductor substrate so as to surround a central circuit strip. A second interconnection frame is provided on first metal interconnection frame with an insulating film therebetween. Both ends of a supply line are in contact with second interconnection frame. There is a gap provided between both ends of a ground line and second interconnection frame. Ground line and first interconnection frame are connected, using a via hole provided in the insulating film. Thus, an improved dynamic random access memory in which the voltage levels of supply lines and ground lines are stabilized is provided.

Abstract: It is an object to obtain a multiplier circuit with reduced circuit scale or with reduced power consumption. Booth decoders (BD1-BD3) receive overlapping three bits of a 6-bit multiplier (Y) (Y0-Y5), respectively, and output partial product information groups (S1-S5) to partial product generating circuits (PP1-PP3) on the basis of the three bits of the multiplier (Y), respectively. Each partial product information is provided in a one-to-one correspondence for each kind of partial product. The partial product generating circuits (PP1-PP3) respectively receive the partial product information groups (S1-S5) from the respective Booth decoders (BD1-BD3) and a 8-bit multiplicand (X) (X0-X7), and output partial products (SM1-SM3) to a partial product adder circuit (ADD1). The partial product adder circuit (ADD1) adds the partial products (SM1-SM3) and outputs a multiplication result (XY) of the multiplier (Y) and the multiplicand (X).

Abstract: A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

Abstract: An electromagnetic contactor to which voltage generated through full wave rectification of an alternating current or DC voltage is loaded. The device provides control for a closing operation with a large pulse width according to a set-up frequency and control for maintaining the closed state of the electromagnetic contactor with a small pulse width for executing ON/OFF control. The device comprises a detector for detecting a peak voltage value of the voltage subjected to full wave rectification and an average value or an effective value thereof and a controller for stabilizing the input at a constant level by controlling a pulse width of a frequency set up based on a voltage value detected by the detector.

Abstract: To improve the clock delay time and skew. A first resistance body (R1) and a second resistance body (R2) are provided at a terminal end node (N5) of a clock trunk line (1) composed of a doped polysilicon film or the like. Their elements (R1), (R2) are composed of the same film as the clock trunk line (1). Their resistance ratio is set so that the clamp level may be an inverted threshold of first and second local drivers (D2, D3), and the resistance values of both resistance bodies (R1, R2), and the value of interconnection resistance (R) of the clock trunk line (1) are set so that an amplitude of a clock signal at each of the nodes (N3, N4, N5) may be a potential corresponding to 1/2 of its peak-to-peak voltage at the same time.

Abstract: A selecting circuit is formed of two tristate gates. The size of each of a plurality of transistors configuring a tristate gate processing a signal having a shorter delay time is set smaller than the size of each of a plurality of transistors configuring a tristate gate processing a signal having a longer delay time, so that the capacitance of the former transistors is decreased. As a result, the load to be driven by each of transistors to which a signal having a longer delay time is applied is decreased, whereby the entire circuit can be increased in operation speed. Accordingly, the selecting circuit selecting between two or more input signals having different delay times can operate at a high speed.

Abstract: It is an object to provide a semiconductor storage device having an optimized sense enable time to reduce unnecessary power consumption. An output node (N1) of a sense amplifier (SA) is connected to an input of a tristate buffer (delay means) (TB) and an output node (N2) of the tristate buffer (TB) is connected to an input of an inverter (I1) forming data holding means (L1). The output nodes (N2 and N3) are connected to inputs of an EXNOR circuit (G1) and an output node (N4) of the EXNOR circuit (G1) is connected to a reset circuit (RS).

Abstract: A semiconductor memory device with low current consumption is disclosed. A bit line selecting circuit (3) establishes electrical connection between a bit line (BL) selected during a read period and a node (N2) in response to bit line connection/selection signals (SB0 to SB4). A charge-up circuit (7) includes PMOS transistors (Q29, Q30). The PMOS transistor (Q29) has a source connected to a power supply (V.sub.DD), a drain connected to a drain of a transistor (Q10) of the bit line selecting circuit (3), and a gate receiving a read control signal (SC). The PMOS transistor (Q30) has a source connected to the power supply (V.sub.DD), a drain connected to the drain of the transistor (Q10) of the bit line selecting circuit (3), and a gate fixed at a ground level.

Abstract: A ring oscillator shortens the delay time between consecutive delayed clock signals, and increases of the number of delayed clock signals, without changing the oscillation frequency f of the ring oscillator and the number of stages n of inverter in one loop, and holding the same control current/osclllation frequency. The ring oscillator has odd numbers of unit inverters, wherein the unit inverter comprises two serial circuits connected in parallel each comprising of P channel transistor and N channel transistor, constant current sources connected to P channel and N channel sides in these parallel circuits, respectively, which are controlled by a current control circuit.

Abstract: It is an object of the present invention to realize bypass of input data in a macro-cell such as a FIFO memory etc. to facilitate test and evaluation about other macro-cells. A bypass route (6) is provided between an input port (DI) and an output port (DO) in a FIFO memory (1) and a data bypassing selector (8) is further provided for selecting the bypass route (6) and a sense amplifier (7) of a read bit line (R.BL). Then, in the test mode, a first selector control signal (S) is set to an L level and a second selector control signal (S) of opposite phase is set to an H level. Thus, in the test mode, a data inputted from the input port (DI) is outputted from the output port (DO) by way of the bypass route (6) without via memory cells (MC1-MCX).

Abstract: Photocurrents outputted by photo detecting circuits (1.sub.1 to 1.sub.n) disposed in first current paths (2.sub.1 to 2.sub.n) are amplified by current amplifying means (3.sub.1 to 3.sub.n) disposed in the first current paths (2.sub.1 to 2.sub.n), respectively. The output currents from the plurality of current amplifying means (3.sub.1 to 3.sub.n) are converted into voltage all by one current-voltage converting means (5). The current amplifying means (3.sub.1 to 3.sub.n) are turned on or off by control signals (3.sub.1S to 3.sub.nS), and therefore the luminance detecting circuit amplifies the current of the required photo detecting element only, and outputs into the current-voltage converting means (5).

Abstract: A programmable controller has a programmable controller unit and a peripheral device which facilitates defining and managing set values of both the internal devices of the programmable controller and the upper and lower limit values by allowing the programmable controller unit and the peripheral device to store set values as reference values for judging the magnitudes of current values of information and updating these values under the control of a sequence program. Further, the programmable controller and peripheral device facilitate the consecutive display, real-time display, etc. of the contents of internal devices by displaying sequentially the contents of these internal devices at predetermined intervals under the control of a sequence program. Additionally this invention allows numerically represented character information stored in internal devices of a programmable controller to be displayed in the form of characters by a simple peripheral device.

Abstract: An inverter operation command apparatus having increase and decrease keys which, when operated according to predetermined requirements, allows the frequency to be set quickly, requires only the increase/decrease key to be actuated to determine the rotation of direction and run/stop of the inverter, and allows the frequency display to be changed. Actuation of increase and decrease keys in predetermined orders, for predetermined durations and at predetermined times, in accordance with predetermined subroutines, will permit flexible control of the inverter frequency.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: In a data reading circuit, an output signal from a sense amplifier which outputs a signal having a level corresponding to a potential difference between an input/output line pair is output through a first tri-state inverter and a second tri-state inverter. An NMOS transistor for precharging is provided between an output node of the first tri-state inverter and an output node (N3) of the sense amplifier. When the sense amplifier and the first tri-state inverter are inactivated, this transistor is also inactivated. As a result, an output node of the second tri-state inverter and an output node of the sense amplifier are connected with this transistor therebetween, so that the output node of the sense amplifier is precharged to an intermediate potential. According to the structure as described above, in the data reading circuit, a fast access is implemented, operation of the circuit is stabilized, and the lack of balance between the access times is suppressed.

Abstract: A positioning apparatus and method for synchronously controlling a plurality of motors, such as servo motors, and exercises synchronous control by means of only motors without using any mechanisms, such as coupling shafts, clutches, gears and cams. A controller has a virtual drive capability which provides a virtual cam and virtual clutch capability on the basis of stored values, permitting continuous and repeated operation of a single cycle of positioning with respect to changes in input axis position address data without recalculation of command addresses in real time.